| Presentation | 2023-07-06 Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware. Honoka Tani, Akira Yamawaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We are developing hardware to realize a high-performance and low-power embedded image processing device using high-level synthesis technology that automatically converts software into hardware. As a first step, the entire processing was divided into former processing and later sub-processing to reduce the size of the target, and software for high-level synthesis was developed for each of these sub-processes, which were then converted into hardware. In this paper, these processes are integrated and executed in parallel to realize the entire process in hardware. The processing time and hardware size of the previous hardware and the integrated hardware were compared, and the performance improvement was confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / FIFO / FPGA |
| Paper # | CAS2023-1,VLD2023-1,SIP2023-17,MSS2023-1 |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | MSS / CAS / SIP / VLD |
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| Conference Date | 2023/7/6(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shingo Yamaguchi(Yamaguchi Univ.) / Yasutoshi Aibara(OmniVision) / Takayuki Nakachi(Ryukyu Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Vice Chair | Toshiyuki Miyamoto(Osaka Inst. of Tech.) / Norihiko Shinomiya(Soka Univ.) / Koichi Ichige(Yokohama National Univ.) / Kiyoshi Nishikawa(okyo Metropolitan Univ.) / Yuichi Sakurai(Hitachi) |
| Secretary | Toshiyuki Miyamoto(Osaka Univ.) / Norihiko Shinomiya(NEC) / Koichi Ichige(Soka Univ.) / Kiyoshi Nishikawa(Renesas Electronics) / Yuichi Sakurai(Chiba Univ.) |
| Assistant | Masato Shirai(Shimane Univ.) / Nao Ito(NIT, Toyama college) / Motoi Yamaguchi(TECHNOPRO) / Shinji Shimoda(Sony Semiconductor Solutions) / Shunsuke Koshita(Hachinohe Inst. of Tech.) / Taichi Yoshida(UEC) / Sayaka Shiota(Tokyo Metropolitan Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Mathematical Systems Science and its Applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware. |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | FIFO |
| Keyword(3) | FPGA |
| 1st Author's Name | Honoka Tani |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2023-07-06 |
| Paper # | CAS2023-1,VLD2023-1,SIP2023-17,MSS2023-1 |
| Volume (vol) | vol.123 |
| Number (no) | CAS-97,VLD-98,SIP-99,MSS-100 |
| Page | pp.pp.1-5(CAS), pp.1-5(VLD), pp.1-5(SIP), pp.1-5(MSS), |
| #Pages | 5 |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) |