Presentation 2023-03-01
High fidelity mask pattern generation method by amplitude component evaluation
Yu Horimoto, Sota Saito, Atsushi Takahashi, Yukihide Kohira, Chikaaki Kodama,
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Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # VLD2022-79,HWS2022-50
Date of Issue 2023-02-22 (VLD, HWS)

Conference Information
Committee HWS / VLD
Conference Date 2023/3/1(4days)
Place (in Japanese) (See Japanese page)
Place (in English)
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Topics (in English)
Chair Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT)
Vice Chair Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu)
Secretary Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS)
Assistant / Takuma Nishimoto(Hitachi)

Paper Information
Registration To Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High fidelity mask pattern generation method by amplitude component evaluation
Sub Title (in English)
Keyword(1)
1st Author's Name Yu Horimoto
1st Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
2nd Author's Name Sota Saito
2nd Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
3rd Author's Name Atsushi Takahashi
3rd Author's Affiliation Tokyo Institute of Technology(Tokyo Tech)
4th Author's Name Yukihide Kohira
4th Author's Affiliation The University of Aizu(Univ. of Aizu)
5th Author's Name Chikaaki Kodama
5th Author's Affiliation KIOXIA Corporation(KIOXIA)
Date 2023-03-01
Paper # VLD2022-79,HWS2022-50
Volume (vol) vol.122
Number (no) VLD-402,HWS-403
Page pp.pp.37-42(VLD), pp.37-42(HWS),
#Pages 6
Date of Issue 2023-02-22 (VLD, HWS)