Presentation	2023-03-02 Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis Masayuki Usui, Shinya Takamaeda,
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Abstract(in English)	We automatically decouple data orchestration mechanisms in explicit data orchestration to facilitate accelerator design. We implemented the proposed method based on the existing high-level synthesis tool Veriloggen. The proposed method reduced execution time by almost half.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Accelerator / High-level synthesis / Memory system
Paper #	VLD2022-90,HWS2022-61
Date of Issue	2023-02-22 (VLD, HWS)

Conference Information
Committee	HWS / VLD
Conference Date	2023/3/1(4days)
Place (in Japanese)	(See Japanese page)
Place (in English)
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Topics (in English)
Chair	Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT)
Vice Chair	Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu)
Secretary	Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS)
Assistant	/ Takuma Nishimoto(Hitachi)

Paper Information
Registration To	Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis
Sub Title (in English)
Keyword(1)	Accelerator
Keyword(2)	High-level synthesis
Keyword(3)	Memory system
1st Author's Name	Masayuki Usui
1st Author's Affiliation	The University of Tokyo(UTokyo)
2nd Author's Name	Shinya Takamaeda
2nd Author's Affiliation	The University of Tokyo(UTokyo)
Date	2023-03-02
Paper #	VLD2022-90,HWS2022-61
Volume (vol)	vol.122
Number (no)	VLD-402,HWS-403
Page	pp.pp.103-108(VLD), pp.103-108(HWS),
#Pages	6
Date of Issue	2023-02-22 (VLD, HWS)