| Presentation | 2023-03-25 Design of Decoded Instruction Cache Takero Magara, Nobuyuki Yamasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In Intel x86 processors, instructions are decoded into instructions for the internal RISC engine, called Micro-Operation (uOP) , and then executed. Once decoded, the μ OP is stored in the μ OP Cache. When it is used again, the power consumption is reduced and the performance is improved by eliminating the fetch and decode processes. In addition, the performance is further improved by dispatching with a wider bandwidth than that of the decoder. On the other hand, in RISC processors, instructions are decoded into control signals. Since this control signal is not stored anywhere, the result of decoding cannot be reused. Therefore, in this study, we designed the Decoded Instruction Cache (DIC) as a uOP Cache for RISC processors. The control signals generated by the decoding are combined into Decoded Instruction and stored in DIC. The fetch and decode processes are omitted and the Decoded Instruction is dispatched, which is expected to reduce power consumption and improve performance. In this paper, we introduced the DIC into the Responsive MultiThreaded Processor (RMTP). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Micro-Operation Cache / Decoded Instruction |
| Paper # | CPSY2022-52,DC2022-111 |
| Date of Issue | 2023-03-16 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2023/3/23(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Amagi Town Disaster Prevention Center (Tokunoshima) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuhiro Tsuchiya(Osaka Univ.) / Michihiro Koibuchi(NII) / Hiroyuki Ochi(Ritsumeikan Univ.) / / Hiroshi Inoue(Nagoya Institute of Technology) |
| Vice Chair | Toshinori Hosokawa(Nihon Univ.) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Toshinori Hosokawa(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Tokyo Inst. of Tech.) / (Meiji Univ.) |
| Assistant | / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Decoded Instruction Cache |
| Sub Title (in English) | |
| Keyword(1) | Micro-Operation Cache |
| Keyword(2) | Decoded Instruction |
| 1st Author's Name | Takero Magara |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Nobuyuki Yamasaki |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2023-03-25 |
| Paper # | CPSY2022-52,DC2022-111 |
| Volume (vol) | vol.122 |
| Number (no) | CPSY-451,DC-452 |
| Page | pp.pp.106-111(CPSY), pp.106-111(DC), |
| #Pages | 6 |
| Date of Issue | 2023-03-16 (CPSY, DC) |