Presentation 2023-03-01
Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test
Daisuke Goeda, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michihiro Shintani,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # VLD2022-74,HWS2022-45
Date of Issue 2023-02-22 (VLD, HWS)

Conference Information
Committee HWS / VLD
Conference Date 2023/3/1(4days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT)
Vice Chair Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu)
Secretary Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS)
Assistant / Takuma Nishimoto(Hitachi)

Paper Information
Registration To Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test
Sub Title (in English)
Keyword(1)
1st Author's Name Daisuke Goeda
1st Author's Affiliation Kyoto Institute of Technology(KIT)
2nd Author's Name Tomoki Nakamura
2nd Author's Affiliation Sony Semiconductor Manufacturing Corporation(SCK)
3rd Author's Name Masuo Kajiyama
3rd Author's Affiliation Sony Semiconductor Manufacturing Corporation(SCK)
4th Author's Name Makoto Eiki
4th Author's Affiliation Sony Semiconductor Manufacturing Corporation(SCK)
5th Author's Name Michihiro Shintani
5th Author's Affiliation Kyoto Institute of Technology(KIT)
Date 2023-03-01
Paper # VLD2022-74,HWS2022-45
Volume (vol) vol.122
Number (no) VLD-402,HWS-403
Page pp.pp.7-12(VLD), pp.7-12(HWS),
#Pages 6
Date of Issue 2023-02-22 (VLD, HWS)