| Presentation | 2023-03-01 Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vectors consisting of thousands to tens of thousands of dimensions. On the other hand, since the main operations of HDC, Bind, Permutation and Bound, require several cycles in the computing unit, it is not necessarily efficient to perform HDC on CPU platform. In this paper, we propose a programmable accelerator specialized for HDC. Our accelerator can execute various tasks at high speed and with low power consumption by cooperating with the CPU. Furthermore, by making it possible to freely select three operations per cycle, our accelerator enables to support any HDC encoding method. Through evaluation experiments with the ARM-v7 processor, we show that the above operations can be accelerated by a maximum of 169 times. We also confirmed that our accelerator can improve the energy-delay product up to 13,469 times in the training of handwritten character recognition task. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hyperdimensional Computing / Hardware accelerator / Domain-specific architecture |
| Paper # | VLD2022-76,HWS2022-47 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2023/3/1(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT) |
| Vice Chair | Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices |
| Sub Title (in English) | |
| Keyword(1) | Hyperdimensional Computing |
| Keyword(2) | Hardware accelerator |
| Keyword(3) | Domain-specific architecture |
| 1st Author's Name | Yuya Isaka |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Nau Sakaguchi |
| 2nd Author's Affiliation | San Jose State University(SJSU) |
| 3rd Author's Name | Michiko Inoue |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 4th Author's Name | Michihiro Shintani |
| 4th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| Date | 2023-03-01 |
| Paper # | VLD2022-76,HWS2022-47 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-402,HWS-403 |
| Page | pp.pp.19-24(VLD), pp.19-24(HWS), |
| #Pages | 6 |
| Date of Issue | 2023-02-22 (VLD, HWS) |