Presentation | 2023-03-14 FPGA implementation of PQC Signature Algorithm QR-UOV using High Level Synthesis Kimihiro Yamakoshi, Tsunekaze Saito, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | QR-UOV has been proposed by Furue et al. as a signature scheme with security tolerance gainst quantum computers. QR-UOV is an improved version of the UOV scheme using multivariate polynomials, and achieves the same level of security with a more compact public key compared to the UOV scheme. In this paper, based on C source code implemented with security level-I parameters, we generated RTL-level code for an FPGA using high-level synthesis and performed logic synthesis. The results of performance evaluation of the circuit and issues to be addressed for speed-up of the circuit are reported. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | PQC / QR-UOV / FPGA / High Level Synthesis |
Paper # | IT2022-92,ISEC2022-71,WBS2022-89,RCC2022-89 |
Date of Issue | 2023-03-07 (IT, ISEC, WBS, RCC) |
Conference Information | |
Committee | RCC / ISEC / IT / WBS |
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Conference Date | 2023/3/14(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | Shunichi Azuma(Nagoya Univ.) / Noboru Kunihiro(Tsukuba Univ.) / Tetsuya Kojima(Tokyo Kosen) / Takashi Shono(Wind River) |
Vice Chair | Shunichi Azuma(Hokkaido Univ.) / Koji Ishii(Kagawa Univ.) / Junji Shikata(Yokohama National Univ.) / Goichiro Hanaoka(AIST) / Yasuyuki Nogami(Okayama Univ.) / Hiroyasu Ishikawa(Nihon Univ.) / Hideki Ochiai(Yokohama National Univ.) |
Secretary | Shunichi Azuma(CRIEPI) / Koji Ishii(Ritsumeikan Univ.) / Junji Shikata(AIST) / Goichiro Hanaoka(Ibaraki Univ.) / Yasuyuki Nogami(Saitamai Univ.) / Hiroyasu Ishikawa(Nagaoka Univ. of Tech.) / Hideki Ochiai(Okayama Prefectural Univ.) |
Assistant | SHAN LIN(NICT) / Ryosuke Adachi(Yamaguchi Univ.) / Yoshikazu Hanatani(Toshiba) / Takayuki Nozaki(Yamaguchi Univ.) / Sun Ran(Ibaraki Univ.) / Chen Na(NAIST) |
Paper Information | |
Registration To | Technical Committee on Reliable Communication and Control / Technical Committee on Information Security / Technical Committee on Information Theory / Technical Committee on Wideband System |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | FPGA implementation of PQC Signature Algorithm QR-UOV using High Level Synthesis |
Sub Title (in English) | |
Keyword(1) | PQC |
Keyword(2) | QR-UOV |
Keyword(3) | FPGA |
Keyword(4) | High Level Synthesis |
1st Author's Name | Kimihiro Yamakoshi |
1st Author's Affiliation | NTT Social Informatics Laboratories(NTT) |
2nd Author's Name | Tsunekaze Saito |
2nd Author's Affiliation | NTT Social Informatics Laboratories(NTT) |
Date | 2023-03-14 |
Paper # | IT2022-92,ISEC2022-71,WBS2022-89,RCC2022-89 |
Volume (vol) | vol.122 |
Number (no) | IT-427,ISEC-428,WBS-429,RCC-430 |
Page | pp.pp.149-154(IT), pp.149-154(ISEC), pp.149-154(WBS), pp.149-154(RCC), |
#Pages | 6 |
Date of Issue | 2023-03-07 (IT, ISEC, WBS, RCC) |