| Presentation | 2023-03-02 [Memorial Lecture] An SMT-Solver-based Synthesis of NNA-Compliant antum Circuits Consisting of CNOT, H and T Gates Kyehei Seino, Shigeru Yamashita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is natural to assume that we can perform quantum operations be-tween only two adjacent physical qubits (quantum bits) to realizea quantum computer for both the current and possible future tech-nologies. This restriction is called the Nearest Neighbor Architec-ture (NNA) restriction. This paper proposes an SMT-solver-basedsynthesis of quantum circuits consisting of CNOT, H, and T gatesto satisfy the NNA restriction. Although the existing SMT-solver-based synthesis cannot treat H and T gates directly, our methodtreats the functionality of quantum-specific T and H gates care-fully so that we can utilize an SMT-solver to minimize the numberof CNOT gates; unlike the existing SMT-solver-based methods, ourmethod considers “Don’t Care” conditions in intermediate pointsof a quantum circuit by exploiting the property of T gates to re-duce CNOT gates. Experimental results show that our approachcan reduce the number of CNOT gates by 58.11% on average com-pared to the naive application of the existing method which doesnot consider the “Don’t Care” condition. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Nearest Neighbor Architecture (NNA) restriction / SMT-Solver / T gate / Don’t Care Condition |
| Paper # | VLD2022-94,HWS2022-65 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2023/3/1(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Makoto Nagata(Kobe Univ.) / Minako Ikeda(NTT) |
| Vice Chair | Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Shigetoshi Nakatake(NBS) |
| Assistant | / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] An SMT-Solver-based Synthesis of NNA-Compliant antum Circuits Consisting of CNOT, H and T Gates |
| Sub Title (in English) | |
| Keyword(1) | Nearest Neighbor Architecture (NNA) restriction |
| Keyword(2) | SMT-Solver |
| Keyword(3) | T gate |
| Keyword(4) | Don’t Care Condition |
| 1st Author's Name | Kyehei Seino |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan University) |
| 2nd Author's Name | Shigeru Yamashita |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan University) |
| Date | 2023-03-02 |
| Paper # | VLD2022-94,HWS2022-65 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-402,HWS-403 |
| Page | pp.pp.112-112(VLD), pp.112-112(HWS), |
| #Pages | 1 |
| Date of Issue | 2023-02-22 (VLD, HWS) |