| Presentation | 2023-02-28 A Novel High Performance Scan-Test-Aware Hardened Latch with Improved Soft Error Tolerability Ruijun Ma, Stefan Holst, Xiaoqing Wen, Hui Xu, Aibin Yan, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The continuous pursuing of smaller technology nodes makes modern Integrated Circuits (ICs) more and more susceptible to soft-errors. Many radiation-hardened latch designs have been proposed to tolerate soft-errors for reliable LSI designs. However, these existing hardened latches can suffer from reliability issues after production because production defects in such hardened latches are difficult to detect with conventional scan testing. In our previous works, we improved the defect detectability of these hardened latches by adding design-for-test (DFT) technique. A hardened latch design, called high performance scan-test-aware hardened latch (HP-STAHL), was proposed for higher defect detectability, higher soft-error tolerability, and lower propagation delay. However, the added DFT structure in HP-STAHL can partially reduce its soft-error tolerability. In this paper, we propose a novel high performance scan-test-aware hardened latch design with improved soft-error tolerability (HP-STAHL-I) by applying a novel design to offset the reduced soft-error tolerability. Simulation results show that HP-STAHL-I provides higher soft-error tolerability than HP-STAHL. HP-STAHL-I also has lower delay and power delay product (PDP) than the standard latch, demonstrating its high performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | soft-errorhardened latchdefectscan test |
| Paper # | DC2022-91 |
| Date of Issue | 2023-02-21 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2023/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuhiro Tsuchiya(Osaka Univ.) |
| Vice Chair | Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Toshinori Hosokawa(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Novel High Performance Scan-Test-Aware Hardened Latch with Improved Soft Error Tolerability |
| Sub Title (in English) | |
| Keyword(1) | soft-errorhardened latchdefectscan test |
| 1st Author's Name | Ruijun Ma |
| 1st Author's Affiliation | Anhui University of Science and Technology(AUST) |
| 2nd Author's Name | Stefan Holst |
| 2nd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 3rd Author's Name | Xiaoqing Wen |
| 3rd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 4th Author's Name | Hui Xu |
| 4th Author's Affiliation | Anhui University of Science and Technology(AUST) |
| 5th Author's Name | Aibin Yan |
| 5th Author's Affiliation | Anhui University(AU) |
| Date | 2023-02-28 |
| Paper # | DC2022-91 |
| Volume (vol) | vol.122 |
| Number (no) | DC-393 |
| Page | pp.pp.51-55(DC), |
| #Pages | 5 |
| Date of Issue | 2023-02-21 (DC) |