Presentation 2023-02-28
Locating Hotspots in a Logic Circuit and Evaluation of Hotspots Caused by an Arbitrary Test Vector
Taiki Utsunomiya, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive delay, resulting in test malfunction. Excessive IR-drop does not occur in the entire area of circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the specific areas. Locating areas where excessive IR-drop occur is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots in a logic circuit by switching probability calculation. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can locate hotspots by comparing the results of power consumption which show hotspots in various areas depending on a test pattern.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) At-speed testing / test power
Paper # DC2022-92
Date of Issue 2023-02-21 (DC)

Conference Information
Committee DC
Conference Date 2023/2/28(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Tatsuhiro Tsuchiya(Osaka Univ.)
Vice Chair Toshinori Hosokawa(Nihon Univ.)
Secretary Toshinori Hosokawa(Nihon Univ.)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Locating Hotspots in a Logic Circuit and Evaluation of Hotspots Caused by an Arbitrary Test Vector
Sub Title (in English)
Keyword(1) At-speed testing
Keyword(2) test power
1st Author's Name Taiki Utsunomiya
1st Author's Affiliation Kyushu Institute of Technology(Kyutech)
2nd Author's Name Kohei Miyase
2nd Author's Affiliation Kyushu Institute of Technology(Kyutech)
3rd Author's Name Shyue-Kung Lu
3rd Author's Affiliation National Taiwan University of Science and Technology(NTUST)
4th Author's Name Xiaoqing Wen
4th Author's Affiliation Kyushu Institute of Technology(Kyutech)
5th Author's Name Seiji Kajihara
5th Author's Affiliation Kyushu Institute of Technology(Kyutech)
Date 2023-02-28
Paper # DC2022-92
Volume (vol) vol.122
Number (no) DC-393
Page pp.pp.56-61(DC),
#Pages 6
Date of Issue 2023-02-21 (DC)