| Presentation | 2023-02-28 A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for Embedded Self-Testing Yangling Xu, Rei Miura, Toshinori Hosokawa, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrated circuits are increasingly suffering from the impact of timing related defects. Therefore, testing for transition faults is necessary. It is important to reduce test cost and improve test quality to deal with the complexity of fault models. To resolve this problem, built-in self-test (BIST) technique is widely used. However, since BIST uses pseudo-random pattern testing, fault coverage is not high due to the existence of random pattern resistant faults. Therefore, in BIST, reseed techniques have been proposed and one-pass seed generation methods which deal with the model combined the functions of the circuit under test and the pseudo-random pattern generator. In this paper, to reduce the number of seeds we use a pseudo-Boolean optimization (PBO) to generate seeds for multiple target faults and PBO maximizes the number of detected target faults. Furthermore, to ensure that the test patterns applied from the generated seed are capture-safe, we propose a one-pass seed generation method for multiple target faults with a power consumption threshold constraint using PBO. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BIST / transition faults / seed generation / Pseudo-Boolean optimization / low power consumption |
| Paper # | DC2022-89 |
| Date of Issue | 2023-02-21 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2023/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuhiro Tsuchiya(Osaka Univ.) |
| Vice Chair | Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Toshinori Hosokawa(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for Embedded Self-Testing |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | transition faults |
| Keyword(3) | seed generation |
| Keyword(4) | Pseudo-Boolean optimization |
| Keyword(5) | low power consumption |
| 1st Author's Name | Yangling Xu |
| 1st Author's Affiliation | Nihon university(Nihon Univ) |
| 2nd Author's Name | Rei Miura |
| 2nd Author's Affiliation | Nihon university(Nihon Univ) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon university(Nihon Univ) |
| 4th Author's Name | Masayoshi Yoshimura |
| 4th Author's Affiliation | Kyoto Sangyo University(KSU) |
| Date | 2023-02-28 |
| Paper # | DC2022-89 |
| Volume (vol) | vol.122 |
| Number (no) | DC-393 |
| Page | pp.pp.39-44(DC), |
| #Pages | 6 |
| Date of Issue | 2023-02-21 (DC) |