| Presentation | 2023-01-23 Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya, Yasunori Osana, Takefumi Miyoshi, Hironori Nakajo, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as artificial intelligence (AI) and high-performance computing (HPC). However, in recent years, these operations have become more enormous and complex, resulting in hardware resource shortages and other problems. To overcome this problem, we have been investigating Reconfigurable Virtual Accelerator (ReVA). In this paper, we describe a prototype of ReVA's circuit distribution, which implements circuits on multiple FPGAs independently of the input design structure by an extension of RapidStream, an open-source HLS automated split compilation tool. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / hardware acceleration / HLS / circuit partitioning |
| Paper # | VLD2022-57,RECONF2022-80 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD |
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| Conference Date | 2023/1/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Kentaro Sano(RIKEN) / Minako Ikeda(NTT) |
| Vice Chair | / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | (Tokyo Inst. of Tech.) / Yoshiki Yamaguchi(Meiji Univ.) / Tomonori Izumi(Sony Semiconductor Solutions) / Shigetoshi Nakatake(HITACHI) |
| Assistant | / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | hardware acceleration |
| Keyword(3) | HLS |
| Keyword(4) | circuit partitioning |
| 1st Author's Name | Kazuki Yaguchi |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 2nd Author's Name | Eriko Maeda |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 3rd Author's Name | Daichi Teruya |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 4th Author's Name | Yasunori Osana |
| 4th Author's Affiliation | University of the Ryukyus(Univ. of the Ryukyus) |
| 5th Author's Name | Takefumi Miyoshi |
| 5th Author's Affiliation | WasaLabo, LLC.(WasaLabo) |
| 6th Author's Name | Hironori Nakajo |
| 6th Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| Date | 2023-01-23 |
| Paper # | VLD2022-57,RECONF2022-80 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-353,RECONF-354 |
| Page | pp.pp.7-12(VLD), pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |