| Presentation | 2023-01-24 Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Binarized neural networks (BNN) allow compact hardware implementation by binarizing weight values and neuron activations. The critical path delay of a combinational circuit implementing a BNN neuron may be curbed by adopting a Wallace tree of full-adders. However, in FPGA implementation, a 3-input full-adder does not make full use of LUTs of more than 5 inputs. This paper proposes the use of a GPC (generalized parallel counter) based compressor tree in FPGA implementation of a BNN neuron to reduce both the delay and size of the resulting circuit. We further enhance the efficiency of the circuit by reducing the comparison of the popcount and threshould into reference to the carry signal from the compressor tree. The critical path delay and the slice count of our BNN neuron, implemented on a Xilinx Artinx-7 FPGA, were smaller by 8.9% and 6.3%, respectively, compared to those of the circuit produced by simplelogic synthesis, at number of inputs 256. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | binarized neural network / BNN / generalized parallel counter / FPGA / compressor tree |
| Paper # | VLD2022-68,RECONF2022-91 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD |
|---|---|
| Conference Date | 2023/1/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Kentaro Sano(RIKEN) / Minako Ikeda(NTT) |
| Vice Chair | / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | (Tokyo Inst. of Tech.) / Yoshiki Yamaguchi(Meiji Univ.) / Tomonori Izumi(Sony Semiconductor Solutions) / Shigetoshi Nakatake(HITACHI) |
| Assistant | / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree |
| Sub Title (in English) | |
| Keyword(1) | binarized neural network |
| Keyword(2) | BNN |
| Keyword(3) | generalized parallel counter |
| Keyword(4) | FPGA |
| Keyword(5) | compressor tree |
| 1st Author's Name | Takahiro Tanigawa |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Mugi Noda |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 3rd Author's Name | Nagisa Ishiura |
| 3rd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2023-01-24 |
| Paper # | VLD2022-68,RECONF2022-91 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-353,RECONF-354 |
| Page | pp.pp.50-55(VLD), pp.50-55(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |