| Presentation | 2023-01-23 Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The SA method is widely used as a logic device placement method for FPGAs. We have introduced neural networks to the placement evaluation of the SA method to obtain better placement. However, there is still room for optimization in the placement evaluation. In this paper, we propose a multi-layered model that combines an autoencoder model, aiming to improve the learning accuracy and placement and routing results. The proposed model improves placement evaluation accuracy by approximately 7% compared to the conventional model. The proposed model can also be applied to the placement evaluation of the SA method to improve the wiring congestion and critical path delay. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / MachineLearning / Placement / CAD |
| Paper # | VLD2022-58,RECONF2022-81 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD |
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| Conference Date | 2023/1/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Kentaro Sano(RIKEN) / Minako Ikeda(NTT) |
| Vice Chair | / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | (Tokyo Inst. of Tech.) / Yoshiki Yamaguchi(Meiji Univ.) / Tomonori Izumi(Sony Semiconductor Solutions) / Shigetoshi Nakatake(HITACHI) |
| Assistant | / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | MachineLearning |
| Keyword(3) | Placement |
| Keyword(4) | CAD |
| Keyword(5) | |
| 1st Author's Name | Junpei Sanuki |
| 1st Author's Affiliation | Hiroshima City University(HCU) |
| 2nd Author's Name | Ibuki Watanabe |
| 2nd Author's Affiliation | Hiroshima City University(HCU) |
| 3rd Author's Name | Atsushi Kubota |
| 3rd Author's Affiliation | Hiroshima City University(HCU) |
| 4th Author's Name | Tetsuo Hironaka |
| 4th Author's Affiliation | Hiroshima City University(HCU) |
| Date | 2023-01-23 |
| Paper # | VLD2022-58,RECONF2022-81 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-353,RECONF-354 |
| Page | pp.pp.13-18(VLD), pp.13-18(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |