| Presentation | 2023-01-24 Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM Motoki Kamibayashi, Kazutoshi Kobayashi, Masanori Hashimoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, as the memory capacity of computer systems has increased,the reliability of the system has decreased.Soft errors are one of the main reasons for the decreased reliability.In this paper, two types of 8Gb DRAM (Dynamic Random Access Memory) were irradiated with neutron beamsto evaluate their soft error tolerance.LPDDR4 SDRAM was used on an FPGA board and GDDR5 SDRAM was used on a GPU board.The results showed that the soft error rates for both DRAMs were around 3 FIT/Gb.In LPDDR4, all of the detected errors were burst errors,and in GDDR5, 38% of the detected errors were burst errors. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft Error / DRAM / Burst Error / FPGA |
| Paper # | VLD2022-65,RECONF2022-88 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD |
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| Conference Date | 2023/1/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Kentaro Sano(RIKEN) / Minako Ikeda(NTT) |
| Vice Chair | / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Secretary | (Tokyo Inst. of Tech.) / Yoshiki Yamaguchi(Meiji Univ.) / Tomonori Izumi(Sony Semiconductor Solutions) / Shigetoshi Nakatake(HITACHI) |
| Assistant | / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM |
| Sub Title (in English) | |
| Keyword(1) | Soft Error |
| Keyword(2) | DRAM |
| Keyword(3) | Burst Error |
| Keyword(4) | FPGA |
| 1st Author's Name | Motoki Kamibayashi |
| 1st Author's Affiliation | Kyoto Institute of Technology(Kyoto Inst. of Tech.) |
| 2nd Author's Name | Kazutoshi Kobayashi |
| 2nd Author's Affiliation | Kyoto Institute of Technology(Kyoto Inst. of Tech.) |
| 3rd Author's Name | Masanori Hashimoto |
| 3rd Author's Affiliation | Kyoto University(Kyoto Univ.) |
| Date | 2023-01-24 |
| Paper # | VLD2022-65,RECONF2022-88 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-353,RECONF-354 |
| Page | pp.pp.34-39(VLD), pp.34-39(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |