| Presentation | 2022-11-28 Development of ASIC Prototype Chip Evaluation System using FPGA-SoM Masashi Imai, Kenji Kise, Tomohiro Yoneda, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of versatility. In this paper, we propose a general ASIC prototype chip evaluation system using FPGA-SoM. An MNIST AI chip which recognizes handwritten digit characters is designed and manufactured for the evaluation of the developed system. We also propose a hardware testbench concept in which the testbench descrptions are directly translated into hardware. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA-SoM / ASIC / AI chip / Hardware test bench |
| Paper # | VLD2022-19,ICD2022-36,DC2022-35,RECONF2022-42 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
|---|---|
| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of ASIC Prototype Chip Evaluation System using FPGA-SoM |
| Sub Title (in English) | |
| Keyword(1) | FPGA-SoM |
| Keyword(2) | ASIC |
| Keyword(3) | AI chip |
| Keyword(4) | Hardware test bench |
| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Kenji Kise |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech.) |
| 3rd Author's Name | Tomohiro Yoneda |
| 3rd Author's Affiliation | National Institute of Informatics(NII) |
| Date | 2022-11-28 |
| Paper # | VLD2022-19,ICD2022-36,DC2022-35,RECONF2022-42 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.1-6(VLD), pp.1-6(ICD), pp.1-6(DC), pp.1-6(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |