Presentation 2022-11-29
Evaluation of power delivery networks in secure semiconductor systems
Masaru Mashiba, Kazuki Monta, Takaaki Okidono, Takuzi Miki, Makoto Nagata,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) With the development of the IoT, hardware security is becoming increasingly important. Physical attacks on cryptoprocessors are a major threat to hardware security in the advanced information society. In this study, we focus on the change in power supply noise caused by physical access by malicious attackers such as side-channel attacks, and aim to detect attacks on hardware by evaluating the power delivery networks and extracting features using on-chip power supply monitoring. In this paper, we report the feature extraction of the power delivery networks of two different evaluation boards and the changes in the features when probes are brought into contact with the power delivery networks.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware Security / Crypto Processors / Side-Channel Attacks / Power Noise / On-Chip Power Monitoring / power delivery networks
Paper # VLD2022-33,ICD2022-50,DC2022-49,RECONF2022-56
Date of Issue 2022-11-21 (VLD, ICD, DC, RECONF)

Conference Information
Committee VLD / DC / RECONF / ICD / IPSJ-SLDM
Conference Date 2022/11/28(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kanazawa Bunka Hall
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2022 -New Field of VLSI Design-
Chair Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.)
Vice Chair Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo)
Secretary Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.)
Assistant Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of power delivery networks in secure semiconductor systems
Sub Title (in English)
Keyword(1) Hardware Security
Keyword(2) Crypto Processors
Keyword(3) Side-Channel Attacks
Keyword(4) Power Noise
Keyword(5) On-Chip Power Monitoring
Keyword(6) power delivery networks
1st Author's Name Masaru Mashiba
1st Author's Affiliation Kobe University(Kobe Univ.)
2nd Author's Name Kazuki Monta
2nd Author's Affiliation Kobe University(Kobe Univ.)
3rd Author's Name Takaaki Okidono
3rd Author's Affiliation SCU Co., Ltd.(SCU)
4th Author's Name Takuzi Miki
4th Author's Affiliation Kobe University(Kobe Univ.)
5th Author's Name Makoto Nagata
5th Author's Affiliation Kobe University(Kobe Univ.)
Date 2022-11-29
Paper # VLD2022-33,ICD2022-50,DC2022-49,RECONF2022-56
Volume (vol) vol.122
Number (no) VLD-283,ICD-284,DC-285,RECONF-286
Page pp.pp.82-86(VLD), pp.82-86(ICD), pp.82-86(DC), pp.82-86(RECONF),
#Pages 5
Date of Issue 2022-11-21 (VLD, ICD, DC, RECONF)