| Presentation | 2022-11-30 Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a boundary scan design with an embedded time-to-digital convertor circuit to detect delay faults in interconnects. A prototype 3D stacked IC with this delay testable circuit was fabricated, and the signal delay that occurred through TSVs was measured. As a result, the proposed delay testable circuit can detect both logic errors that occurred in TSVs with smaller than standard diameters and significant signal delay through a TSV with no logic error. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TSV(Through Silicon via) / delay fault / design for testability |
| Paper # | VLD2022-47,ICD2022-64,DC2022-63,RECONF2022-70 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC |
| Sub Title (in English) | |
| Keyword(1) | TSV(Through Silicon via) |
| Keyword(2) | delay fault |
| Keyword(3) | design for testability |
| 1st Author's Name | Keigo Takami |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ. Univ.) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2022-11-30 |
| Paper # | VLD2022-47,ICD2022-64,DC2022-63,RECONF2022-70 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.162-167(VLD), pp.162-167(ICD), pp.162-167(DC), pp.162-167(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |