| Presentation | 2022-11-28 On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have been proposed for approximate multipliers by truncating the lower bits of the calculation result according to the positions of one-bits in the multiplier and the multiplicand. In testing approximation circuits, test time reduction can possibly be achieved by removing faults that affect only within the acceptable range of the calculation error. In this paper, to generate fewer test patterns for an approximate multiplier, the pseudo circuit restricting the fault propagation only to the lower bits is added in the test generation phase. As a result, the proposed test generation can attain about a 19.8% reduction in test patterns. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test pattern generation / approximate computing / multiplier / test time reduction |
| Paper # | VLD2022-23,ICD2022-40,DC2022-39,RECONF2022-46 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On reduction of test patterns for a Multiplier Using Approximate Computing |
| Sub Title (in English) | |
| Keyword(1) | test pattern generation |
| Keyword(2) | approximate computing |
| Keyword(3) | multiplier |
| Keyword(4) | test time reduction |
| 1st Author's Name | Shogo Tokai |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ) |
| 2nd Author's Name | Daichi Akamatsu |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ) |
| 3rd Author's Name | Hiroyuki Yotsuyanagi |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ) |
| 4th Author's Name | Masaki Hashizume |
| 4th Author's Affiliation | Tokushima University(Tokushima Univ) |
| Date | 2022-11-28 |
| Paper # | VLD2022-23,ICD2022-40,DC2022-39,RECONF2022-46 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.25-30(VLD), pp.25-30(ICD), pp.25-30(DC), pp.25-30(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |