| Presentation | 2022-11-30 Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | $DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low frequency by $DeltaSigma$ modulation. However, it requires narrow PLL bandwidth. This paper proposes the method to design higher-order $DeltaSigma$ FDC-PLLs by applying multi-stage noise shaping (MASH). The proposed PLLs can make in-band quantization noise lower than that of conventional FDC-PLLs , which enables more flexible loop optimization. The proposed PLL is designed in 65,nm CMOS process using 3bit SAR ADC and a $DeltaSigma$ ADC. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Phase locked loop(PLL) / $DeltaSigma$ frequency-to-digital converter(FDC) / multi-stage noise shaping(MASH) / quantization noise |
| Paper # | VLD2022-43,ICD2022-60,DC2022-59,RECONF2022-66 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise |
| Sub Title (in English) | |
| Keyword(1) | Phase locked loop(PLL) |
| Keyword(2) | $DeltaSigma$ frequency-to-digital converter(FDC) |
| Keyword(3) | multi-stage noise shaping(MASH) |
| Keyword(4) | quantization noise |
| 1st Author's Name | Ryoga Iwashita |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Zule Xu |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| 3rd Author's Name | Masaru Osada |
| 3rd Author's Affiliation | The University of Tokyo(UTokyo) |
| 4th Author's Name | Ryoya Shibata |
| 4th Author's Affiliation | The University of Tokyo(UTokyo) |
| 5th Author's Name | Yo Kumano |
| 5th Author's Affiliation | The University of Tokyo(UTokyo) |
| 6th Author's Name | Tetsuya Iizuka |
| 6th Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2022-11-30 |
| Paper # | VLD2022-43,ICD2022-60,DC2022-59,RECONF2022-66 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.138-143(VLD), pp.138-143(ICD), pp.138-143(DC), pp.138-143(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |