| Presentation | 2022-11-30 On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by combining a delay testable circuit based on boundary scan design and a PUF (physicallyunclonable function) circuit. We have already confirmed that the unique values generated by the proposed circuit can be utilized as a PUF. However, it is not evaluated whether the proposed circuit can be available as a PUF under temperature variations. In this paper, we investigate the prototype IC under varying temperatures and evaluate the generated unique values for evaluating PUF performance. The results show that the proposed circuit has both high uniqueness and stability. We also confirmed the generated unique values can achieve the individual identification ofchips. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PUF / delay tesing using design-for-testability / unanimous selection method / individual identification / temperature variation |
| Paper # | VLD2022-46,ICD2022-63,DC2022-62,RECONF2022-69 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects |
| Sub Title (in English) | |
| Keyword(1) | PUF |
| Keyword(2) | delay tesing using design-for-testability |
| Keyword(3) | unanimous selection method |
| Keyword(4) | individual identification |
| Keyword(5) | temperature variation |
| 1st Author's Name | Eisuke Ohama |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2022-11-30 |
| Paper # | VLD2022-46,ICD2022-63,DC2022-62,RECONF2022-69 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.156-161(VLD), pp.156-161(ICD), pp.156-161(DC), pp.156-161(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |