| Presentation | 2022-11-30 Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops Daiki Yokoyama, Kimiyoshi Usami, Aika Kamei, Hideharu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | LSI has been developed by miniaturization, but the increase in leakage power caused by it has become a problem. Non-volatile power gating (NVPG) using a Magnetic Tunnel Junction (MTJ) is one of techniques for reducing leakage power. Two Step Store (TSS), which is one of the NVPG control methods and executes short store and then executes long store only for those elements that could not be written, is a method for improving process variation, temperature change, and probabilistic effects of MTJ. Energy can be greatly reduced when the shortest store success time differs from cell to cell depending on behavior. However, the characteristics of the optimal store time that minimizes the total store energy under TSS control have not been clarified. In this study, we clarify the physical and statistical parameters that affect the optimal store time, and compare and evaluate using real silicon chips. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MTJ / Power-Gating / TSS / Analytical expression |
| Paper # | VLD2022-39,ICD2022-56,DC2022-55,RECONF2022-62 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops |
| Sub Title (in English) | |
| Keyword(1) | MTJ |
| Keyword(2) | Power-Gating |
| Keyword(3) | TSS |
| Keyword(4) | Analytical expression |
| 1st Author's Name | Daiki Yokoyama |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 3rd Author's Name | Aika Kamei |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2022-11-30 |
| Paper # | VLD2022-39,ICD2022-56,DC2022-55,RECONF2022-62 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.115-120(VLD), pp.115-120(ICD), pp.115-120(DC), pp.115-120(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |