| Presentation | 2022-11-30 Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Logic elements of FPGA generally use Look-Up Table (LUT) circuits, and the most common types of LUT are 4-input and 6-input due to area efficiency. We proposed a 4-input Variable Logic Circuit with FGC using neuron CMOS inverters (4 in VLC) as an alternative circuit to the 4-input LUT, and verified the FGC and variable logic operation of the 4 in VLC using HSPICE simulations. In this paper, we make a prototype chip of the 4 in VLC with Rohm 0.18um process, evaluate the FGC operation and variable logic operation, and compare the simulation results with the actual device behavior. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neuron CMOS inverter / Variable Logic Circuit / FPGA |
| Paper # | VLD2022-45,ICD2022-62,DC2022-61,RECONF2022-68 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter |
| Sub Title (in English) | |
| Keyword(1) | Neuron CMOS inverter |
| Keyword(2) | Variable Logic Circuit |
| Keyword(3) | FPGA |
| 1st Author's Name | Shoma Ito |
| 1st Author's Affiliation | Tokai University(Tokai Univ.) |
| 2nd Author's Name | Daishi Nishiguchi |
| 2nd Author's Affiliation | Tokai University(Tokai Univ.) |
| 3rd Author's Name | Masaaki Fukuhara |
| 3rd Author's Affiliation | Tokai University(Tokai Univ.) |
| Date | 2022-11-30 |
| Paper # | VLD2022-45,ICD2022-62,DC2022-61,RECONF2022-68 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.150-155(VLD), pp.150-155(ICD), pp.150-155(DC), pp.150-155(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |