| Presentation | 2022-11-29 FPGA-based Accelerators System with Autonomous DMA Engine Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, computing systems have comprised specialized computing components such as FPGAs, GPUs, and various ASIC accelerators to enhance efficiency and performance. We proposed a queue structure mechanism to communicate between CPUs-FPGAs and offload tasks onto FPGAs asynchronously. This paper presents an FPGA system with an autonomous DMA engine to enhance efficiency and performance. We build the system installed in eight FPGAs in which a customized DMA engine is implemented and evaluate communication performance including Software Stack for a single FPGA and the communication latency of an FPGA chain. In a single FPGA, oursystem achieves DMA read bandwidth of up to 68.5% and DMA write bandwidth of up to 62.2% for PCIe Gen3 x16 theoretical performance. An FPGA chain of up to 8 FPGAs in 4MB data size has latency of 3.7 milliseconds, which under half that when using the existing DMA method(7.6 milliseconds). |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2022-28,ICD2022-45,DC2022-44,RECONF2022-51 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2022/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kanazawa Bunka Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Chair | Minako Ikeda(NTT) / Tatsuhiro Tsuchiya(Osaka Univ.) / Kentaro Sano(RIKEN) / Masafumi Takahashi(Kioxia) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Toshinori Hosokawa(Nihon Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Shigetoshi Nakatake(NBS) / Toshinori Hosokawa(Hirosaki Univ.) / Yoshiki Yamaguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Makoto Ikeda(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA-based Accelerators System with Autonomous DMA Engine |
| Sub Title (in English) | |
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| 1st Author's Name | Tomoya Yokono |
| 1st Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 2nd Author's Name | Yoshiro Yamabe |
| 2nd Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 3rd Author's Name | Kenji Tanaka |
| 3rd Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 4th Author's Name | Yuki Arikawa |
| 4th Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 5th Author's Name | Teruaki Ishizaki |
| 5th Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| Date | 2022-11-29 |
| Paper # | VLD2022-28,ICD2022-45,DC2022-44,RECONF2022-51 |
| Volume (vol) | vol.122 |
| Number (no) | VLD-283,ICD-284,DC-285,RECONF-286 |
| Page | pp.pp.55-60(VLD), pp.55-60(ICD), pp.55-60(DC), pp.55-60(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |