| Presentation | 2022-10-25 Hardware Acceleration of TFHE-based Adder by Controlling Error Yinfan Zhao, Ikeda Makoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the Fully homomorphic encryption over Torus (TFHE) is the fastest in all FHE schemes now, so compared with BGV scheme TFHE is more friendly in deep leveled computation situations. However, the speed of TFHE-based operation is too slow. For example, the TFHE-based 32-bit addition needs 2.9s. This design focuses on improving the speed of TFHE-based addition by new hardware structures. We propose an error-controlled method to construct bigger multi-input-output gates. Now, it is possible to build a 5-input gate with the same security level. Then, we optimize the process of blind rotation. Last, we optimize the key switching process to make the key smaller. The size of the new key switching key is 277 times smaller than the original one. From RTL simulation, a 32-bits TFHE-based adder will use 84.3ms, 34 times faster than the original scheme. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fully homomorphic encryption / TFHE / TFHE-based adders / Hardware accelerators / Error controlled |
| Paper # | HWS2022-40,ICD2022-32 |
| Date of Issue | 2022-10-18 (HWS, ICD) |
| Conference Information | |
| Committee | HWS / ICD |
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| Conference Date | 2022/10/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Chair | Makoto Nagata(Kobe Univ.) / Masafumi Takahashi(Kioxia) |
| Vice Chair | Yuichi Hayashi(NAIST) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Secretary | Yuichi Hayashi(Sony Semiconductor Solutions) / Daisuke Suzuki(NAIST) / Makoto Ikeda(TSMC) |
| Assistant | / Yoshiaki Yoshihara(KIOXIA) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Acceleration of TFHE-based Adder by Controlling Error |
| Sub Title (in English) | |
| Keyword(1) | Fully homomorphic encryption |
| Keyword(2) | TFHE |
| Keyword(3) | TFHE-based adders |
| Keyword(4) | Hardware accelerators |
| Keyword(5) | Error controlled |
| 1st Author's Name | Yinfan Zhao |
| 1st Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Ikeda Makoto |
| 2nd Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| Date | 2022-10-25 |
| Paper # | HWS2022-40,ICD2022-32 |
| Volume (vol) | vol.122 |
| Number (no) | HWS-227,ICD-228 |
| Page | pp.pp.58-63(HWS), pp.58-63(ICD), |
| #Pages | 6 |
| Date of Issue | 2022-10-18 (HWS, ICD) |