| Presentation | 2022-10-11 Low power quantized neural network by reducing the operating voltage of SRAM Ji Wu, Kazuteru Namba, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the advancement of artificial intelligence technologies, neural networks have been attracting attention as a machine learning technique that provides superior performance in image recognition. Since high-precision neural network computing inevitably requires enormous computational resources and power consumption, there are challenges in integrating neural networks into edge devices with limited memory and power consumption. Therefore, to reduce the computational load, research has been conducted to quantize neural network operations, which are composed of many multiplications and additions, to a low-bit number and to execute them on dedicated hardware such as AIoT (Artificial Intelligence of Things). In this paper, we propose an SRAM based on high-voltage and low-voltage modes to store the weights of the quantized neural network. In general, quantization of neural networks and lowering the operating voltage of SRAM reduce the recognition accuracy rate. We investigated the relationship between the two operations mentioned above and the recognition accuracy rate. We proposed a circuit model that can lower power consumption while maintaining a high recognition rate. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Quantization / Neural Networks / SRAM |
| Paper # | CPSY2022-20,DC2022-20 |
| Date of Issue | 2022-10-04 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2022/10/11(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Yuzawa Toei Hotel |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Architecture, Computer Systems, Dependable Computing, etc. |
| Chair | Michihiro Koibuchi(NII) / Tatsuhiro Tsuchiya(Osaka Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Vice Chair | Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Kota Nakajima(JAIST) / Tomoaki Tsumura(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / (Chiba Univ.) |
| Assistant | Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low power quantized neural network by reducing the operating voltage of SRAM |
| Sub Title (in English) | |
| Keyword(1) | Quantization |
| Keyword(2) | Neural Networks |
| Keyword(3) | SRAM |
| 1st Author's Name | Ji Wu |
| 1st Author's Affiliation | Chiba University(Chiba Univ) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University(Chiba Univ) |
| Date | 2022-10-11 |
| Paper # | CPSY2022-20,DC2022-20 |
| Volume (vol) | vol.122 |
| Number (no) | CPSY-204,DC-205 |
| Page | pp.pp.14-19(CPSY), pp.14-19(DC), |
| #Pages | 6 |
| Date of Issue | 2022-10-04 (CPSY, DC) |