Presentation | 2022-09-08 FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | |
Paper # | RECONF2022-33 |
Date of Issue | 2022-08-31 (RECONF) |
Conference Information | |
Committee | RECONF |
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Conference Date | 2022/9/7(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | emCAMPUS STUDIO |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Reconfigurable system, etc. |
Chair | Kentaro Sano(RIKEN) |
Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) |
Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.) |
Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) |
Paper Information | |
Registration To | Technical Committee on Reconfigurable Systems |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA |
Sub Title (in English) | |
Keyword(1) | |
1st Author's Name | Yasuhiro Nakahara |
1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
2nd Author's Name | Yuta Masuda |
2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
3rd Author's Name | Masato Kiyama |
3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
4th Author's Name | Masahiro Iida |
4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
Date | 2022-09-08 |
Paper # | RECONF2022-33 |
Volume (vol) | vol.122 |
Number (no) | RECONF-174 |
Page | pp.pp.23-28(RECONF), |
#Pages | 6 |
Date of Issue | 2022-08-31 (RECONF) |