| Presentation | 2022-09-29 Analog circuit implementation of spiking neural networks and its application to time-series information processing Satoshi Moriya, Hideaki Yamamoto, Yasushi Yuminaka, Shigeo Sato, Yoshihiko Horio, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Edge computing in which low-dimensional signals such as sensor output are processed nearby sensors have become increasingly important. Spiking neural networks (SNNs), which simulate the dynamics of neural circuits, have attracted attention as a suitable information processing technology for edge computing due to their efficiency to handle not only spatial information but also temporal information. In this study, we designed and fabricated neuron circuits and SNN circuits that reproduce neural spikes with low power consumption by taking advantage of the analog characteristics of CMOS transistors. We found that the complex neural spikes were reproduced with power consumption of less than 100 fJ/spike. We also applied the framework of reservoir computation to spike trains obtained from SNN circuits and showed that the proposed circuits can be applied to time series information processing. These results contribute to the realization of low-power edge devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | spiking neuron / spiking neural networks / analog circuit |
| Paper # | NC2022-33 |
| Date of Issue | 2022-09-22 (NC) |
| Conference Information | |
| Committee | NC / MBE |
|---|---|
| Conference Date | 2022/9/29(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Brain Architecture, NC, ME |
| Chair | Hiroshi Yamakawa(Univ of Tokyo) / Junichi Hori(Niigata Univ.) |
| Vice Chair | Hirokazu Tanaka(Tokyo City Univ.) / Hisashi Yoshida(Kinki Univ.) |
| Secretary | Hirokazu Tanaka(NTT) / Hisashi Yoshida(NICT) |
| Assistant | Yoshimasa Tawatsuji(Waseda Univ.) / Tomoki Kurikawa(KMU) / Emi Yuda(Tohoku Univ) / Miki Kaneko(Osaka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Neurocomputing / Technical Committee on ME and Bio Cybernetics |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analog circuit implementation of spiking neural networks and its application to time-series information processing |
| Sub Title (in English) | |
| Keyword(1) | spiking neuron |
| Keyword(2) | spiking neural networks |
| Keyword(3) | analog circuit |
| 1st Author's Name | Satoshi Moriya |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ) |
| 2nd Author's Name | Hideaki Yamamoto |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ) |
| 3rd Author's Name | Yasushi Yuminaka |
| 3rd Author's Affiliation | Gunma University(Gunma Univ.) |
| 4th Author's Name | Shigeo Sato |
| 4th Author's Affiliation | Tohoku University(Tohoku Univ) |
| 5th Author's Name | Yoshihiko Horio |
| 5th Author's Affiliation | Tohoku University(Tohoku Univ) |
| Date | 2022-09-29 |
| Paper # | NC2022-33 |
| Volume (vol) | vol.122 |
| Number (no) | NC-195 |
| Page | pp.pp.5-5(NC), |
| #Pages | 1 |
| Date of Issue | 2022-09-22 (NC) |