| Presentation | 2022-08-08 [Invited Talk] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur Zule Xu, Masaru Osada, Tetsuya Iizuka, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present a type-II fractional-N hybrid switched-capacitor sampling PLL, using a capacitive digital-to-analog converter (CDAC) as a sampler and an analog adder receiving the digital integrator’s output. To guarantee sufficient CDAC settling time and filter switch-on time, we designed a synchronous timing generator utilizing the multi-modulus divider’s (MMDIV’s) inter-stage clocks. The prototype chip in 65-nm CMOS achieves −80-dBc reference spur, 236-fs integrated RMS jitter, and 4.6-mW power consumption, translating to −246-dB FoM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hybrid PLLsampling PLLfractional-NCDAC |
| Paper # | SDM2022-43,ICD2022-11 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
|---|---|
| Conference Date | 2022/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic) |
| Assistant | Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur |
| Sub Title (in English) | |
| Keyword(1) | hybrid PLLsampling PLLfractional-NCDAC |
| 1st Author's Name | Zule Xu |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Masaru Osada |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| 3rd Author's Name | Tetsuya Iizuka |
| 3rd Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2022-08-08 |
| Paper # | SDM2022-43,ICD2022-11 |
| Volume (vol) | vol.122 |
| Number (no) | SDM-148,ICD-149 |
| Page | pp.pp.41-44(SDM), pp.41-44(ICD), |
| #Pages | 4 |
| Date of Issue | 2022-08-01 (SDM, ICD) |