| Presentation | 2022-08-08 Evaluation of Low-Latency Cryptography MANTIS based Low-Power oriented Tamper-Resistant Circuit Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Lightweight cryptography can not only be implemented in a small area, but also with low latency and low power consumption. Therefore, they are suitable for use in IoT devices Among them, MANTIS, a low-latency cryptography, is more resistant to related-key attack than conventional light-weight cryptography by using a tuning value called “Tweak”. On the other hand, side-channel attacks have been conducted against MANTIS using selected plaintexts, making tamper resistance an issue. This study evaluates the effectiveness of a tamper resistance and low-power-consumption countermeasure circuit based on the low-latency cryptosystem MANTIS by implementing it on an FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware Security / Lightweight Block Cipher / MANTIS / Tamper Resistance |
| Paper # | SDM2022-41,ICD2022-9 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2022/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic) |
| Assistant | Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Low-Latency Cryptography MANTIS based Low-Power oriented Tamper-Resistant Circuit |
| Sub Title (in English) | |
| Keyword(1) | Hardware Security |
| Keyword(2) | Lightweight Block Cipher |
| Keyword(3) | MANTIS |
| Keyword(4) | Tamper Resistance |
| 1st Author's Name | Kosuke Hamaguchi |
| 1st Author's Affiliation | Meijo University(Meijo Univ.) |
| 2nd Author's Name | Shu Takemoto |
| 2nd Author's Affiliation | Meijo University(Meijo Univ.) |
| 3rd Author's Name | Yusuke Nozaki |
| 3rd Author's Affiliation | Meijo University(Meijo Univ.) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijo University(Meijo Univ.) |
| Date | 2022-08-08 |
| Paper # | SDM2022-41,ICD2022-9 |
| Volume (vol) | vol.122 |
| Number (no) | SDM-148,ICD-149 |
| Page | pp.pp.31-36(SDM), pp.31-36(ICD), |
| #Pages | 6 |
| Date of Issue | 2022-08-01 (SDM, ICD) |