| Presentation | 2022-08-08 Evaluation of IC Chip Response by Backside Voltage Disturbance in Flip Chip Packaging Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Flip chip packaging has become a general technique for mounting semiconductor ICs due to the need for smaller area. However, the exposed backside of the IC can cause EMC problems such as permanent or temporary failures due to exposure to all kinds of disturbances. Furthermore, the risk of physical attacks that exploit EMC vulnerabilities is also considered to increase. In this study, a prototype chip was fabricated to quantitatively evaluate backside voltage disturbances. The prototype chip is equipped with an on-chip monitoring circuit created with a SAR ADC, which enables measurement of silicon substrate voltages at multiple locations. Voltage disturbances were actually injected from the backside, and the voltage waveforms on the chip surface and their position dependence were confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Flip Chip Packaging / SAR ADC / Disturbance / Fault Injection |
| Paper # | SDM2022-40,ICD2022-8 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2022/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic) |
| Assistant | Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of IC Chip Response by Backside Voltage Disturbance in Flip Chip Packaging |
| Sub Title (in English) | |
| Keyword(1) | Flip Chip Packaging |
| Keyword(2) | SAR ADC |
| Keyword(3) | Disturbance |
| Keyword(4) | Fault Injection |
| 1st Author's Name | Takuya Wadatsumi |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Kohei Kawai |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Rikuu Hasegawa |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| 4th Author's Name | Kikuo Muramatsu |
| 4th Author's Affiliation | e-SYNC Co., Ltd.(e-SYNC) |
| 5th Author's Name | Hiromu Hasegawa |
| 5th Author's Affiliation | MegaChips Corp.(Megachips) |
| 6th Author's Name | Takuya Sawada |
| 6th Author's Affiliation | MegaChips Corp.(Megachips) |
| 7th Author's Name | Takahito Fukushima |
| 7th Author's Affiliation | MegaChips Corp.(Megachips) |
| 8th Author's Name | Hisashi Kondo |
| 8th Author's Affiliation | MegaChips Corp.(Megachips) |
| 9th Author's Name | Takuji Miki |
| 9th Author's Affiliation | Kobe University(Kobe Univ.) |
| 10th Author's Name | Makoto Nagata |
| 10th Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2022-08-08 |
| Paper # | SDM2022-40,ICD2022-8 |
| Volume (vol) | vol.122 |
| Number (no) | SDM-148,ICD-149 |
| Page | pp.pp.27-30(SDM), pp.27-30(ICD), |
| #Pages | 4 |
| Date of Issue | 2022-08-01 (SDM, ICD) |