Presentation 2022-08-08
[Invited Talk] Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors
Naohiko Kimizuka, Shota Kitamura, Akiko Honjo, Koichi Baba, Toshihiro Kurobe, Hideomi Kumano, Takuya Toyohuku, Kouhei Takeuchi, Shota Nishimura, Akihiko Kato, Tomoyuki Hirano, Yusuke Oike,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The pixel size of CMOS image sensor (CIS) continues to be rapidly decreasing due to strong demand from mobile applications. As a result, the area in which the pixel transistor can be integrated also decrease, making it difficult to maintain the transistor size (channel length and width). In particular, the pixel transistor size of a source follower (SF) amplifier determines the noise performance. Therefore, at this time, we propose a new low-noise multi-gate pixel transistor, specially customized for an SF amplifier of CIS. The random telegraph signal (RTS) noise and 1/f noise have been improved by maximizing the effective channel width and by not performing impurity doping into the channel. Compared to a conventional planar-type pixel transistor with same footprint, RTS noise and 1/f noise have been reduced by 91% and 43%, respectively. The transconductance has been improved by 43%, which contributes to reduce thermal noise. We could evaluate imaging characteristics using a prototype with 0.7?m pixel, having new multi-gate pixel transistor we have developed. It was revealed that proposed multi-gate structure dedicated to pixel transistor is a promising candidate to solve issues emerging from pixel size shrinkage.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) pixel transistor / RTS noise / 1/f noise / multi-gate structure
Paper # SDM2022-34,ICD2022-2
Date of Issue 2022-08-01 (SDM, ICD)

Conference Information
Committee ICD / SDM / ITE-IST
Conference Date 2022/8/8(3days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications
Chair Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大)
Vice Chair Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック)
Secretary Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic)
Assistant Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Invited Talk] Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors
Sub Title (in English)
Keyword(1) pixel transistor
Keyword(2) RTS noise
Keyword(3) 1/f noise
Keyword(4) multi-gate structure
1st Author's Name Naohiko Kimizuka
1st Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
2nd Author's Name Shota Kitamura
2nd Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
3rd Author's Name Akiko Honjo
3rd Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
4th Author's Name Koichi Baba
4th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
5th Author's Name Toshihiro Kurobe
5th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
6th Author's Name Hideomi Kumano
6th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
7th Author's Name Takuya Toyohuku
7th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
8th Author's Name Kouhei Takeuchi
8th Author's Affiliation Sony Semiconductor Manufacturing(Sony Semiconductor Manufacturing)
9th Author's Name Shota Nishimura
9th Author's Affiliation Sony Semiconductor Manufacturing(Sony Semiconductor Manufacturing)
10th Author's Name Akihiko Kato
10th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
11th Author's Name Tomoyuki Hirano
11th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
12th Author's Name Yusuke Oike
12th Author's Affiliation Sony Semiconductor Solutions(Sony Semiconductor Solutions)
Date 2022-08-08
Paper # SDM2022-34,ICD2022-2
Volume (vol) vol.122
Number (no) SDM-148,ICD-149
Page pp.pp.7-7(SDM), pp.7-7(ICD),
#Pages 1
Date of Issue 2022-08-01 (SDM, ICD)