| Presentation | 2022-08-08 Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori, Koichiro Ishibashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we report the first prototype results of a Steep SS "Dual-Gate (DG) PN-Body Tied (PNBT) SOI-FET" for extremely low-voltage operation. In our laboratory, we have proposed a "PN-Body Tied (PNBT) SOI-FET" with a steep Subthreshold Slope (SS) to realize CMOS integrated circuits with extremely low power consumption. However, it has been found that the PNBT SOI-FET requires a body voltage of about 0.7 V or higher to obtain a steep SS. It is also known that leakage current flows during turn-off. To solve these problems, a new structure of "Dual-Gate (DG) type PNBT SOI-FET" was proposed in our laboratory. As a result, we confirmed steep SS even in the DG-type PNBT SOI-FET. It was also found that the 1st gate voltage, which triggers steep SS, can be controlled by the 2nd gate. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SOI-FET / Steep Subthreshold Slope |
| Paper # | SDM2022-38,ICD2022-6 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2022/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic) |
| Assistant | Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Steep Subthreshold Slope Device "Dual-gate type PN-body Tied SOI-FET" for Ultra-low Voltage Operation |
| Sub Title (in English) | |
| Keyword(1) | SOI-FET |
| Keyword(2) | Steep Subthreshold Slope |
| 1st Author's Name | Haruki Yonezaki |
| 1st Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 2nd Author's Name | Jiro Ida |
| 2nd Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 3rd Author's Name | Takayuki Mori |
| 3rd Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 4th Author's Name | Koichiro Ishibashi |
| 4th Author's Affiliation | The University of Electro-Communications(UEC) |
| Date | 2022-08-08 |
| Paper # | SDM2022-38,ICD2022-6 |
| Volume (vol) | vol.122 |
| Number (no) | SDM-148,ICD-149 |
| Page | pp.pp.17-20(SDM), pp.17-20(ICD), |
| #Pages | 4 |
| Date of Issue | 2022-08-01 (SDM, ICD) |