| Presentation | 2022-08-10 IC with Integrated Imager and Ultra-Low Latency All-Digital In-Imager 2D Binary Convolutional Neural Network Accelerator for Image Classification Wang Ruizhi, Takamiya Makoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the field of real-time image recognition, the computing latency of convolutional neural network become an issue. In this paper, we propose an all-digital in-imager 2D binary convolutional neural network (II2D-BNN) architecture for low-latency convolutional neural network computation. In II2D-BNN, multiply-accumulate operations (MACs) are processed inside the imager array parallelly in 2D, which makes convolutional operations be realized with ultra-low latency independent of input image size. A 30 × 30 II2D-BNN accelerator IC integrating imager circuit is fabricated with the 180 nm CMOS process. It achieved a 3.22 μs/kernel latency on the first layer convolution at the power supply of 1 V and the clock frequency of 35.7 MHz, reducing 80.5 % of latency compared with the state-of-the-art in/near-imager-computing work. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Convolutional neural network / Ultra-low-latency / Batch-processing-in-2D / In-imager-computing / Image classification |
| Paper # | SDM2022-53,ICD2022-21 |
| Date of Issue | 2022-08-01 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2022/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Masafumi Takahashi(Kioxia) / Shunichiro Ohmi(Tokyo Inst. of Tech.) / 秋田 純一(金沢大) |
| Vice Chair | Makoto Ikeda(Univ. of Tokyo) / Tatsuya Usami(ASM Japan) / 池辺 将之(北大) / 廣瀬 裕(パナソニック) |
| Secretary | Makoto Ikeda(Shinshu Univ.) / Tatsuya Usami(TSMC) / 池辺 将之(Tohoku Univ.) / 廣瀬 裕(Panasonic) |
| Assistant | Jun Shiomi(Osaka Univ.) / Yoshiaki Yoshihara(キオクシア) / Takeshi Kuboki(Sony Semiconductor Solutions) / Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(SanDisk) / 山下 雄一郎(TSMC) / 大倉 俊介(立命館大) / 竹本 良章(メムスコア) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | IC with Integrated Imager and Ultra-Low Latency All-Digital In-Imager 2D Binary Convolutional Neural Network Accelerator for Image Classification |
| Sub Title (in English) | |
| Keyword(1) | Convolutional neural network |
| Keyword(2) | Ultra-low-latency |
| Keyword(3) | Batch-processing-in-2D |
| Keyword(4) | In-imager-computing |
| Keyword(5) | Image classification |
| 1st Author's Name | Wang Ruizhi |
| 1st Author's Affiliation | University of Tokyo(The Univ. of Tokyo) |
| 2nd Author's Name | Takamiya Makoto |
| 2nd Author's Affiliation | University of Tokyo(The Univ. of Tokyo) |
| Date | 2022-08-10 |
| Paper # | SDM2022-53,ICD2022-21 |
| Volume (vol) | vol.122 |
| Number (no) | SDM-148,ICD-149 |
| Page | pp.pp.87-92(SDM), pp.87-92(ICD), |
| #Pages | 6 |
| Date of Issue | 2022-08-01 (SDM, ICD) |