| Presentation | 2022-07-29 Efficient placement of coherence directories in memory networks Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Michihiro Koibuchi, Hidearu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Memory Cube (MC) is a memory module that manages three-dimensional stacking of DRAM chips with a logic layer on the bottom layer. The logic layer has a routing function and can route packets to their destinations. Therefore, a Memory-centric Network (MCN) has been proposed to construct a memory network by interconnecting multiple MCs. However, the number of message hops and latency for coherence management are larger in MCNs than in conventional networks that directly connect processors. In conventional MCNs, the coherence directory, which manages data coherence, is assumed to be located in the processor. However, if the coherence directory is placed in the processor, when accessing an MC that is not managed by itself from the processor's point of view, it is necessary to access another processor to check the sharer information. This can be an overhead, especially for write accesses where invalidation signals and ACK communication occur. Therefore, we propose a method in which a coherence directory is placed in the logic layer of the MC and the MC manages the coherence of its own data. This eliminates the need to access other processors to check the sharer information and reduces the number of message hops and latency for coherence management. Evaluation with synthetic traffic and real applications showed that the proposed method can reduce the number of cycles by about 15% for synthetic traffic and by about 25% for real applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Memory Cube / Memory Network / Coherence Directory / Memory-centric Network / HMC |
| Paper # | CPSY2022-14,DC2022-14 |
| Date of Issue | 2022-07-20 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2022/7/27(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kaikyo Messe Shimonoseki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SWoPP2022: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Michihiro Koibuchi(NII) / Tatsuhiro Tsuchiya(Osaka Univ.) / 津邑 公暁(名工大) |
| Vice Chair | Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Kota Nakajima(JAIST) / Tomoaki Tsumura(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / (Chiba Univ.) |
| Assistant | Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient placement of coherence directories in memory networks |
| Sub Title (in English) | |
| Keyword(1) | Memory Cube |
| Keyword(2) | Memory Network |
| Keyword(3) | Coherence Directory |
| Keyword(4) | Memory-centric Network |
| Keyword(5) | HMC |
| 1st Author's Name | Yuki Kameyama |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Naoya Niwa |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Daichi Fujiki |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Michihiro Koibuchi |
| 4th Author's Affiliation | National Institute of Informatics(NII) |
| 5th Author's Name | Hidearu Amano |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2022-07-29 |
| Paper # | CPSY2022-14,DC2022-14 |
| Volume (vol) | vol.122 |
| Number (no) | CPSY-133,DC-134 |
| Page | pp.pp.77-82(CPSY), pp.77-82(DC), |
| #Pages | 6 |
| Date of Issue | 2022-07-20 (CPSY, DC) |