| Presentation | 2022-07-28 Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai, Takuya Kojima, Hayate Okuhara, Masahiro Iida, Hideharu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FPGA/CPU SoC has been attracting attention. Instead of the conventional high-end mixed SoC with large area and power consumption, a compact and low-power mixed SoC combining a relatively small microprocessor and an embedded FPGA IP, eFPGA (Embedded FPGA), has already been discussed as an effective solution. Based on this, we are developing SLMLET, a new compact and low-power SoC for IoT edge devices that combines SLM (Scalable Logic Module) reconfigurable logic developed by Kumamoto University, RISC-V CPU, SRAM, and external I/F. SLM has a small amount of bitstream size and small logic cells, and RISC-V CPUs are characterized by their small size and the existence of many open-source implementations. This paper introduces the SLMLET chip and evaluates the DMA transfer performance between SLMLETs using Hyperbus, a high-speed interface between the chips, as a pre-production evaluation. The results showed that when the Hyperbus controller was operated at 50 MHz, which is the assumed speed for logic synthesis, transfers of 1024 bytes or more exceeded 90% of the maximum bandwidth, and transfers of 65535 bytes, the maximum size supported by the controller, exceeded 99.9% of the maximum bandwidth, 799.4Mbps was confirmed to be achievable. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RISC-V / eFPGA / SLM Reconfigurable Logic / Mixed SoC |
| Paper # | CPSY2022-8,DC2022-8 |
| Date of Issue | 2022-07-20 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2022/7/27(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kaikyo Messe Shimonoseki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SWoPP2022: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Michihiro Koibuchi(NII) / Tatsuhiro Tsuchiya(Osaka Univ.) / 津邑 公暁(名工大) |
| Vice Chair | Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Kota Nakajima(JAIST) / Tomoaki Tsumura(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / (Chiba Univ.) |
| Assistant | Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic |
| Sub Title (in English) | |
| Keyword(1) | RISC-V |
| Keyword(2) | eFPGA |
| Keyword(3) | SLM Reconfigurable Logic |
| Keyword(4) | Mixed SoC |
| 1st Author's Name | Yosuke Yanai |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Takuya Kojima |
| 2nd Author's Affiliation | Tokyo University(Tokyo Univ.) |
| 3rd Author's Name | Hayate Okuhara |
| 3rd Author's Affiliation | National University of Singapore(NUS.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Hideharu Amano |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2022-07-28 |
| Paper # | CPSY2022-8,DC2022-8 |
| Volume (vol) | vol.122 |
| Number (no) | CPSY-133,DC-134 |
| Page | pp.pp.41-46(CPSY), pp.41-46(DC), |
| #Pages | 6 |
| Date of Issue | 2022-07-20 (CPSY, DC) |