Presentation | 2022-06-07 Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi, Kiyofumi Tanaka, Yasunori Osana, Takefumi Miyoshi, Jubee Tada, Hironori Nakajo, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor with the acceleration circuitry.Since this mechanism can share the value of a vector register at a time, high speed communication is expected, especially in SoC FPGAs. To validate this mechanism, this paper designs and implements a processor with vector registers to get a preliminary evaluation. The RISC-V’s RV64IMV and proprietary instructions are adopted for the instruction set of the proposed processor. As a preliminary evaluation of our proposed architecture, we have measured the CPI, the maximum operating frequency as well as the resource usage with / without vector extension instructions for the processor. The evaluation shows that the proposed processor can transfer data at a maximum of 787.2 [MByte/s] with the vector register sharing mechanism. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | RISC-V / Hardware Acceleration / FPGA / SoC |
Paper # | RECONF2022-5 |
Date of Issue | 2022-05-31 (RECONF) |
Conference Information | |
Committee | RECONF |
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Conference Date | 2022/6/7(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | CCS, Univ. of Tsukuba |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Reconfigurable system, etc. |
Chair | Kentaro Sano(RIKEN) |
Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) |
Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.) |
Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) |
Paper Information | |
Registration To | Technical Committee on Reconfigurable Systems |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Vector Register Sharing Mechanism for Hardware Acceleration |
Sub Title (in English) | |
Keyword(1) | RISC-V |
Keyword(2) | Hardware Acceleration |
Keyword(3) | FPGA |
Keyword(4) | SoC |
1st Author's Name | Tomoaki Tanaka |
1st Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
2nd Author's Name | Ryousuke Higashi |
2nd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
3rd Author's Name | Kiyofumi Tanaka |
3rd Author's Affiliation | Japan Advanced institute of Science and Technology(JAIST) |
4th Author's Name | Yasunori Osana |
4th Author's Affiliation | University of the Ryukyus(Univ. of the Ryukyus) |
5th Author's Name | Takefumi Miyoshi |
5th Author's Affiliation | Wasalabo, LLC.(Wasalabo) |
6th Author's Name | Jubee Tada |
6th Author's Affiliation | Yamagata University(Yamagata Univ.) |
7th Author's Name | Hironori Nakajo |
7th Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
Date | 2022-06-07 |
Paper # | RECONF2022-5 |
Volume (vol) | vol.122 |
Number (no) | RECONF-60 |
Page | pp.pp.26-31(RECONF), |
#Pages | 6 |
Date of Issue | 2022-05-31 (RECONF) |