| Presentation | 2022-06-10 Common-mode voltage reduction by controlling parasitic impedance around three-phase inverter circuit with consideration of load circuit Taiki Kai, Tohlu Matsushima, Yuki Fukumoto, Kohei Takada, Koji Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, as switching devices have increased in switching speed, electromagnetic disturbances generated from power electronic equipment have also become broadband. When electromagnetic noise in the high frequency range is reduced by common mode filters, parasitic coupling of the devices must be considered, thus making it difficult to use higher frequencies in EMC design. Therefore, a common mode voltage reduction based on the impedance balance method has been proposed in the past. By considering parasitic capacitance near switching elements and parasitic inductance of the power supply system as design variables, common mode voltage can be reduced. On the other hand, the effect on the load side of power electronic equipment has not been well considered. In this report, we developed an equivalent circuit model that deals only with common mode and verified the effect of common mode voltage reduction in a three-phase inverter circuit when the impedance of the load side is considered. Circuit calculations show that when the common-mode impedance on the load side is low, the effect of reducing the common-mode voltage by adjusting the parasitic capacitance near the switching device is reduced. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Three-phase inverter circuit / common mode voltage / parasitic coupling |
| Paper # | EMCJ2022-15 |
| Date of Issue | 2022-06-03 (EMCJ) |
| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2022/6/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Atsuhiro Nishikata(Tokyo Inst. of Tech.) |
| Vice Chair | Kimihiro Tajima(NTT-AT) |
| Secretary | Kimihiro Tajima(NAIST) |
| Assistant | Kiyoto Matsushima(Hitachi) / Hiroyoshi Shida(EMC Tech.) / Toru Matsushima(Kyushu Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Electromagnetic Compatibility |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Common-mode voltage reduction by controlling parasitic impedance around three-phase inverter circuit with consideration of load circuit |
| Sub Title (in English) | |
| Keyword(1) | Three-phase inverter circuit |
| Keyword(2) | common mode voltage |
| Keyword(3) | parasitic coupling |
| 1st Author's Name | Taiki Kai |
| 1st Author's Affiliation | SANDEN(SANDEN) |
| 2nd Author's Name | Tohlu Matsushima |
| 2nd Author's Affiliation | SANDEN(SANDEN) |
| 3rd Author's Name | Yuki Fukumoto |
| 3rd Author's Affiliation | SANDEN(SANDEN) |
| 4th Author's Name | Kohei Takada |
| 4th Author's Affiliation | SANDEN(SANDEN) |
| 5th Author's Name | Koji Kobayashi |
| 5th Author's Affiliation | SANDEN(SANDEN) |
| Date | 2022-06-10 |
| Paper # | EMCJ2022-15 |
| Volume (vol) | vol.122 |
| Number (no) | EMCJ-67 |
| Page | pp.pp.5-10(EMCJ), |
| #Pages | 6 |
| Date of Issue | 2022-06-03 (EMCJ) |