| Presentation | 2022-06-09 Hardware Implementation of Annealing Machine using Chaotic Boltzmann Machine Kanta Yoshioka, Ichiro Kawashima, Hakaru Tamukoh, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the end of Moore's law, annealing quantum computers that can solve various combinatorial optimization problems are attracting attention as next-generation computers. However, since quantum computers require large-scale computer facilities, the implementation of annealing machines using digital circuits and their commercial use are gaining popularity. In this study, we implemented an annealing machine using a chaotic Boltzmann machine, a model that is advantageous for hardware implementation. As a result, we implemented 2048 nodes, which is the largest implementation on a single FPGA board and found that it runs about 2.5 times faster than CPUs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Simulated Annealing / FPGA |
| Paper # | SIS2022-1 |
| Date of Issue | 2022-06-02 (SIS) |
| Conference Information | |
| Committee | SIS / IPSJ-AVM |
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| Conference Date | 2022/6/9(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | KIT(Wakamatsu Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Intelligent Multimedia Systems, Applied Embedded Systems, Three-Dimensional Image Technology (3DIT), etc. |
| Chair | Noriaki Suetake(Yamaguchi Univ.) / Sei Naito(KDDI Research, Inc.) |
| Vice Chair | Tomoaki Kimura(Kanagawa Inst. of Tech.) / Naoto Sasaoka(Tottori Univ.) |
| Secretary | Tomoaki Kimura(NTT) / Naoto Sasaoka(National Inst. of Tech., Ube College) / (NTT) |
| Assistant | Soh Yoshida(Kansai Univ.) / Yoshiaki Makabe(Kanagawa Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Smart Info-Media Systems / Special Interest Group on Audio Visual and Multimedia Information Processing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementation of Annealing Machine using Chaotic Boltzmann Machine |
| Sub Title (in English) | |
| Keyword(1) | Simulated Annealing |
| Keyword(2) | FPGA |
| 1st Author's Name | Kanta Yoshioka |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Ichiro Kawashima |
| 2nd Author's Affiliation | Kyushu Institute of Technology/Research Center for Neuromorphic AI Hardware(Kyutech/Neumorph Center) |
| 3rd Author's Name | Hakaru Tamukoh |
| 3rd Author's Affiliation | Kyushu Institute of Technology/Research Center for Neuromorphic AI Hardware(Kyutech/Neumorph Center) |
| Date | 2022-06-09 |
| Paper # | SIS2022-1 |
| Volume (vol) | vol.122 |
| Number (no) | SIS-62 |
| Page | pp.pp.1-6(SIS), |
| #Pages | 6 |
| Date of Issue | 2022-06-02 (SIS) |