| Presentation | 2022-06-08 Consideration of speeding up AI inference processing by cooperative operation of hardware and software Tomoya Kawakami, Chikako Nakanishi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When cooperative processing of AI inference processing between software and hardware, it is difficult to analyze network structures in the Python language, so cooperative processing is not possible. Therefore, we extracted the network information from the learned model and executed it in the C++ language to achieve cooperative operation on a SoCFPGA board and speed up the process. EfficientNetB0 was selected as the target network, and a circuit that enables general-purpose parallel high-speed processing was designed for the convolutional layer (Conv2D layer), which accounts for approximately 90% of the processing time on the CPU. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC FPGA / higher synthesis / EfficientNet / convolutional operation / Ultra96-V2 |
| Paper # | RECONF2022-14 |
| Date of Issue | 2022-05-31 (RECONF) |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2022/6/7(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | CCS, Univ. of Tsukuba |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Kentaro Sano(RIKEN) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Consideration of speeding up AI inference processing by cooperative operation of hardware and software |
| Sub Title (in English) | |
| Keyword(1) | SoC FPGA |
| Keyword(2) | higher synthesis |
| Keyword(3) | EfficientNet |
| Keyword(4) | convolutional operation |
| Keyword(5) | Ultra96-V2 |
| 1st Author's Name | Tomoya Kawakami |
| 1st Author's Affiliation | Osaka Institute of Technology(OIT) |
| 2nd Author's Name | Chikako Nakanishi |
| 2nd Author's Affiliation | Osaka Institute of Technology(OIT) |
| Date | 2022-06-08 |
| Paper # | RECONF2022-14 |
| Volume (vol) | vol.122 |
| Number (no) | RECONF-60 |
| Page | pp.pp.57-62(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-05-31 (RECONF) |