Presentation 2022-06-08
A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration
Li Qi, Li Hengyi, Meng Lin,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Convolutional Neural Networks (CNNs) have achieved high performance and are widely used in various applications. However, CNN's are computational-intensive and resource-consuming, causing the development of CNN applications is limited especially in the embedded systems. Therefore, we propose a dynamic CNN pruning method based on redundant computational analysis. The proposal aims to realize model compression within the setting performance degradation through dynamic iterative channel pruning. Experimental results show the proposal reduces about 80% of parameters and FLOPS. Furthermore, the compacted CNN model is implemented on the FPGA and achieved about 40% speedup in inference time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Convolutional neural network / Channel pruning / Redundant calculation analysis / FPGA
Paper # RECONF2022-21
Date of Issue 2022-05-31 (RECONF)

Conference Information
Committee RECONF
Conference Date 2022/6/7(2days)
Place (in Japanese) (See Japanese page)
Place (in English) CCS, Univ. of Tsukuba
Topics (in Japanese) (See Japanese page)
Topics (in English) Reconfigurable system, etc.
Chair Kentaro Sano(RIKEN)
Vice Chair Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.)
Secretary Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.)
Assistant Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.)

Paper Information
Registration To Technical Committee on Reconfigurable Systems
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration
Sub Title (in English)
Keyword(1) Convolutional neural network
Keyword(2) Channel pruning
Keyword(3) Redundant calculation analysis
Keyword(4) FPGA
1st Author's Name Li Qi
1st Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
2nd Author's Name Li Hengyi
2nd Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
3rd Author's Name Meng Lin
3rd Author's Affiliation Ritsumeikan University(Ritsumeikan Univ.)
Date 2022-06-08
Paper # RECONF2022-21
Volume (vol) vol.122
Number (no) RECONF-60
Page pp.pp.89-94(RECONF),
#Pages 6
Date of Issue 2022-05-31 (RECONF)