Presentation 2022-04-21
A High Process Portability All Digital Time domain A/D Converter
Takahiro Amada, Cong-Kha Pham,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) An all digital time domain A/D converter that can be largely synthesized has been proposed. The proposed circuit was designed using 0.18um CMOS process. This proposed circuit improves high process portability and a significant reduction in design time by designing the majority of the digital circuit using verilog HDL instead of a full-custom design. Simulation results show that the proposed circuit achieves ENOB: 3.04 and power consumption: 1.76mW for a 4-bit A/D converter.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Time domain A/D converter, / TDC / Relative placement / Small circuit area / Low power consumption
Paper # ED2022-6
Date of Issue 2022-04-14 (ED)

Conference Information
Committee ED
Conference Date 2022/4/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Hiroki Fujishiro(Tokyo Univ. of Science)
Vice Chair Seiya Sakai(Hokkaido Univ.)
Secretary Seiya Sakai(Fjitsu Lab.)
Assistant Ryota Isonoi(SCIOCS) / Yoshitugu Yamamoto(Mitsubishi Electric)

Paper Information
Registration To Technical Committee on Electron Devices
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High Process Portability All Digital Time domain A/D Converter
Sub Title (in English)
Keyword(1) Time domain A/D converter,
Keyword(2) TDC
Keyword(3) Relative placement
Keyword(4) Small circuit area
Keyword(5) Low power consumption
1st Author's Name Takahiro Amada
1st Author's Affiliation The University of Electro-Communications(UEC Tokyo)
2nd Author's Name Cong-Kha Pham
2nd Author's Affiliation The University of Electro-Communications(UEC Tokyo)
Date 2022-04-21
Paper # ED2022-6
Volume (vol) vol.122
Number (no) ED-7
Page pp.pp.19-22(ED),
#Pages 4
Date of Issue 2022-04-14 (ED)