| Presentation | 2022-03-07 Improved placement-method of standard cells considering parallel routing Takeru Furuyashiki, Kunihiro Fujiyoshi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, a minimal fab has been proposed for the purpose of small-quantity production of LSI at low cost and in a short period of time, and a minimal EDA using the open-source tool Qflow has been developed. Since the time required is too long for practical, research on speeding up by parallel processing was conducted. However, since the placement tool Graywolf in Qflow does not assume parallel processing of routing, there was a case where the efficiency of parallel processing was low because there was no suitable division. Therefore, we propose a placement method in which the circuit and area are divided by the minimum cut to the number of parallel processes, and then the placement optimization is performed twice by SA in each area in order to shorten the wire length. Before the second placement optimization, pseudo terminals are placed by the global routing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | standard cell / placement / parallel processing / minimal fab |
| Paper # | VLD2021-76,HWS2021-53 |
| Date of Issue | 2022-02-28 (VLD, HWS) |
| Conference Information | |
| Committee | VLD / HWS |
|---|---|
| Conference Date | 2022/3/7(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Yasuhisa Shimazaki(Renesas Electronics) |
| Vice Chair | Minako Ikeda(NTT) / Makoto Nagata(Kobe Univ.) / Daisuke Suzuki(Mitsubishi Electric) |
| Secretary | Minako Ikeda(Osaka Univ.) / Makoto Nagata(NEC) / Daisuke Suzuki(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improved placement-method of standard cells considering parallel routing |
| Sub Title (in English) | |
| Keyword(1) | standard cell |
| Keyword(2) | placement |
| Keyword(3) | parallel processing |
| Keyword(4) | minimal fab |
| 1st Author's Name | Takeru Furuyashiki |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 2nd Author's Name | Kunihiro Fujiyoshi |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| Date | 2022-03-07 |
| Paper # | VLD2021-76,HWS2021-53 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-412,HWS-413 |
| Page | pp.pp.1-6(VLD), pp.1-6(HWS), |
| #Pages | 6 |
| Date of Issue | 2022-02-28 (VLD, HWS) |