Presentation 2022-03-11
Imprecise Mixed Criticality Scheduling for SMT Processor
Reo Nagura, Nobuyuki Yamasaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recently, in the field of real-time scheduling, scheduling methods for mixed-criticality (MC) systems, in which tasks of different criticality are mixed, have been studied. In an MC system, if a high-criticality task does not complete its execution even after the expected execution time, the system mode switches to emergency mode, then low-criticality tasks are dropped for high-criticality tasks. On the other hand, scheduling methods for imprecise computation model, which divides tasks into mandatory parts and optional parts, have been studied. In the imprecise computation model, when the system is overloaded, it is possible to maintain a minimum execution quality by giving high priority to the mandatory part of the task. In this study, we propose the Imprecise Mixed Criticality (IMC) system, which combines the above two methods. In the IMC system, the system is able to maintain the minimum quality of execution even in emergency or overload situations.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Real-Time System / Processor Scheduling
Paper # CPSY2021-63,DC2021-97
Date of Issue 2022-03-03 (CPSY, DC)

Conference Information
Committee CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2022/3/10(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) ETNET2021
Chair Michihiro Koibuchi(NII) / Hiroshi Takahashi(Ehime Univ.) / Yuichi Nakamura(NEC) / / Hiroshi Inoue(Kyushu Univ.)
Vice Chair Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Tatsuhiro Tsuchiya(Osaka Univ.)
Secretary Kota Nakajima(JAIST) / Tomoaki Tsumura(Hitachi) / Tatsuhiro Tsuchiya(Nihon Univ.) / (Chiba Univ.) / (Tokyo City Univ.) / (Tokyo Inst. of Tech.)
Assistant Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Imprecise Mixed Criticality Scheduling for SMT Processor
Sub Title (in English)
Keyword(1) Real-Time System
Keyword(2) Processor Scheduling
1st Author's Name Reo Nagura
1st Author's Affiliation Keio University(Keio Univ.)
2nd Author's Name Nobuyuki Yamasaki
2nd Author's Affiliation Keio University(Keio Univ.)
Date 2022-03-11
Paper # CPSY2021-63,DC2021-97
Volume (vol) vol.121
Number (no) CPSY-425,DC-426
Page pp.pp.109-114(CPSY), pp.109-114(DC),
#Pages 6
Date of Issue 2022-03-03 (CPSY, DC)