Presentation 2022-03-01
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato, Yousuke Miyake, Seiji Kajihara,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the delay value with other values measured in different time, the delay value should be corrected because the circuit delay is affected by variation of temperature and voltage in field measurement. In the previous work correction was done by using temperature and voltage values computed with an on-chip sensor, however it had a problem that correction errors are accumulated through the complex calculation process. This paper proposes a new correction method to eliminate temperature and voltage effects from measured delay values with ring-oscillators. In addition, a calibration method for reducing correction errors is proposed, and finally evaluation results with TEG chips in 65nm CMOS process shows effectiveness of the proposed methods.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Delay measurement / In-field test / Logic BIST / Degradation detection / Ring-Oscillator
Paper # DC2021-67
Date of Issue 2022-02-22 (DC)

Conference Information
Committee DC
Conference Date 2022/3/1(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Hiroshi Takahashi(Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya(Osaka Univ.)
Secretary Tatsuhiro Tsuchiya(Nihon Univ.)

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Sub Title (in English)
Keyword(1) Delay measurement
Keyword(2) In-field test
Keyword(3) Logic BIST
Keyword(4) Degradation detection
Keyword(5) Ring-Oscillator
1st Author's Name Takaaki Kato
1st Author's Affiliation Kyushu Institute of Technology(KIT)
2nd Author's Name Yousuke Miyake
2nd Author's Affiliation PRIVATECH Inc.(PRIVATECH)
3rd Author's Name Seiji Kajihara
3rd Author's Affiliation Kyushu Institute of Technology(KIT)
Date 2022-03-01
Paper # DC2021-67
Volume (vol) vol.121
Number (no) DC-388
Page pp.pp.18-23(DC),
#Pages 6
Date of Issue 2022-02-22 (DC)