| Presentation | 2022-03-07 [Memorial Lecture] An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Lingxiao Hou, Yutaka Masuda, Tohru Ishihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The logarithmic approximate multiplier proposed by Mitchell provides an efficient alternative to accurate multipliers in terms of area and power consumption. However, its maximum error of 11.1% makes it difficult to deploy in applications requiring high accuracy. To widely reduce the error of the Mitchell multiplier, this paper proposes a novel operand decomposition method which decomposes one operand into multiple operands and calculates them using multiple Mitchell multipliers. Based on this operand decomposition, this paper also proposes an accuracy reconfigurable vector accelerator which can provide a required computational accuracy with a high parallelism. The proposed vector accelerator dramatically reduces the area by more than half from the accurate multiplier array while satisfying the required accuracy for various applications. The experimental results show that our proposed vector accelerator behaves well in image processing and robot localization. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Approximate ComputingEnergy Efficient ComputingLow Power DesignVector AccelerationSingle Instruction Multiple Data |
| Paper # | VLD2021-83,HWS2021-60 |
| Date of Issue | 2022-02-28 (VLD, HWS) |
| Conference Information | |
| Committee | VLD / HWS |
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| Conference Date | 2022/3/7(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Yasuhisa Shimazaki(Renesas Electronics) |
| Vice Chair | Minako Ikeda(NTT) / Makoto Nagata(Kobe Univ.) / Daisuke Suzuki(Mitsubishi Electric) |
| Secretary | Minako Ikeda(Osaka Univ.) / Makoto Nagata(NEC) / Daisuke Suzuki(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Memorial Lecture] An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers |
| Sub Title (in English) | |
| Keyword(1) | Approximate ComputingEnergy Efficient ComputingLow Power DesignVector AccelerationSingle Instruction Multiple Data |
| 1st Author's Name | Lingxiao Hou |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 2nd Author's Name | Yutaka Masuda |
| 2nd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| 3rd Author's Name | Tohru Ishihara |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| Date | 2022-03-07 |
| Paper # | VLD2021-83,HWS2021-60 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-412,HWS-413 |
| Page | pp.pp.43-43(VLD), pp.43-43(HWS), |
| #Pages | 1 |
| Date of Issue | 2022-02-28 (VLD, HWS) |