| Presentation | 2022-03-01 Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs．During LSI testing, the power consumption increases due to more switching activities than in normal operation, and then excessive IR-drop occurs. When excessive IR-drop occurs, excessive delays which may lead to test malfunction even if circuits with no problems in normal operation Therefore, in order to avoid test malfunction, it is necessary to apply appropriate techniques before LSI testing is conducted. Excessive IR-drop does not occur in the entire circuit, but in areas where switching activities are densely concentrated．Therefore, in order to effectively reduce excessive IR-drops, it is important to locate areas where switching activity densely occurs．In this paper, we present the method to locate areas where many switching activities occur with switching probabilities of logic gates, and then we evaluate its effectiveness and efficiency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | At-speed testing / test power / transition delay test / IR-drop / test malfunction |
| Paper # | DC2021-73 |
| Date of Issue | 2022-02-22 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2022/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroshi Takahashi(Ehime Univ.) |
| Vice Chair | Tatsuhiro Tsuchiya(Osaka Univ.) |
| Secretary | Tatsuhiro Tsuchiya(Nihon Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability |
| Sub Title (in English) | |
| Keyword(1) | At-speed testing |
| Keyword(2) | test power |
| Keyword(3) | transition delay test |
| Keyword(4) | IR-drop |
| Keyword(5) | test malfunction |
| 1st Author's Name | Ryu Hoshino |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Taiki Utsunomiya |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Kohei Miyase |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 4th Author's Name | Xiaoqing Wen |
| 4th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 5th Author's Name | Seiji Kajihara |
| 5th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2022-03-01 |
| Paper # | DC2021-73 |
| Volume (vol) | vol.121 |
| Number (no) | DC-388 |
| Page | pp.pp.51-56(DC), |
| #Pages | 6 |
| Date of Issue | 2022-02-22 (DC) |