| Presentation | 2022-02-22 Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction Kohei Shinyamada, Akira Yamawaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real camera. The hardware was developed using high-level synthesis. We evaluated the performance of the developed hardware alone, and found that the performance was 166 fps for the image size QVGA and the number of time-series images N=4. The hardware processing was superior in terms of power efficiency when compared to the embedded CPU. However, since the frame rate of the camera used in the prototype was approximately 12 fps, the maximum frame rate of the entire system was approximately 12 fps. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / High-Level Synthesis / HLS / Image Processing / Real Camera System |
| Paper # | ITS2021-61,IE2021-70 |
| Date of Issue | 2022-02-14 (ITS, IE) |
| Conference Information | |
| Committee | IE / ITS / ITE-AIT / ITE-ME / ITE-MMS |
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| Conference Date | 2022/2/21(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Image Processing, etc. |
| Chair | Kazuya Kodama(NII) / Masahiro Fujii(Utsunomiya Univ.) / Hisaki Nate(Tokyo Polytechnic Univ.) / Hiroyuki Arai(Nippon Inst. of Tech.) / Kenji Machida(NHK) |
| Vice Chair | Hiroyuki Bandoh(NTT) / Toshihiko Yamazaki(Univ. of Tokyo) / Kohei Ohno(Meiji Univ.) / Naohisa Hashimoto(AIST) / / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Bandoh(KDDI Research) / Toshihiko Yamazaki(Nagoya Inst. of Tech.) / Kohei Ohno(Akita Prefectural Univ.) / Naohisa Hashimoto(NIT, Tsuruoka College) / / Shogo Muramatsu(NHK) / (Hokkaido Univ.) |
| Assistant | Shunsuke Iwamura(NHK) / Shinobu Kudo(NTT) / Msataka Imao(Mitsubishi Electric) / Kenshi Saho(Toyama Prefectural Univ.) / Keiji Jimi(Gunma Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Image Engineering / Technical Committee on Intelligent Transport Systems Technology / Technical Group on Artistic Image Technology / Technical Group on Media Engineering / Technical Group on Multi-media Storage |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | High-Level Synthesis |
| Keyword(3) | HLS |
| Keyword(4) | Image Processing |
| Keyword(5) | Real Camera System |
| 1st Author's Name | Kohei Shinyamada |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2022-02-22 |
| Paper # | ITS2021-61,IE2021-70 |
| Volume (vol) | vol.121 |
| Number (no) | ITS-373,IE-374 |
| Page | pp.pp.214-218(ITS), pp.214-218(IE), |
| #Pages | 5 |
| Date of Issue | 2022-02-14 (ITS, IE) |