Presentation 2022-01-24
Ternarizing Deep Spiking Neural Network
Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The feasibility of ternarizing spiking neural networks (SNNs) is studied in this work toward trading a slight accuracy for significantly reducing computational and memory costs. By leveraging a parametric integrate-and-fire (PIF) neuron with learnable threshold and spike-timing-dependent backpropagation (STDB) learning rule, the ternarized spiking neural networks (TSNNs) enable directly trained with low latency and negligible loss of accuracy. To this end, a paradigm for binary-ternary dotproduct operation is realized during the inference; therefore, the TSNNs achieve up to 16x model compression in contrast to the full precision SNNs. Moreover, to mitigate the accuracy gap, an optimized TSNN with a spiking ResNet structure is introduced into TSNN. For proof-of-concept, we evaluate the prototype of proposed TSNN on N-MNIST, CIFAR-10, CIFAR-100, which achieve 98.43%, 89.07%, 65.24% accuracy with 4 timesteps, respectively. On the basis of this prototype, the optimized TSNN improves by 0.84% and 0.51% over CIFAR-10 and CIFAR-100 datasets, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) deep spiking neural network / ternary weights / SNN compression / TSNN
Paper # VLD2021-61,CPSY2021-30,RECONF2021-69
Date of Issue 2022-01-17 (VLD, CPSY, RECONF)

Conference Information
Committee RECONF / VLD / CPSY / IPSJ-ARC / IPSJ-SLDM
Conference Date 2022/1/24(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Online
Topics (in Japanese) (See Japanese page)
Topics (in English) FPGA Applications, etc.
Chair Kentaro Sano(RIKEN) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC)
Vice Chair Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Minako Ikeda(NTT) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.)
Secretary Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) / Minako Ikeda(Osaka Univ.) / Kota Nakajima(NEC) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Univ. of Tokyo)
Assistant Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.)

Paper Information
Registration To Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Ternarizing Deep Spiking Neural Network
Sub Title (in English)
Keyword(1) deep spiking neural network
Keyword(2) ternary weights
Keyword(3) SNN compression
Keyword(4) TSNN
1st Author's Name Man Wu
1st Author's Affiliation Nara Institute of Science and Technology(NAIST)
2nd Author's Name Yirong Kan
2nd Author's Affiliation Nara Institute of Science and Technology(NAIST)
3rd Author's Name Van_Tinh Nguyen
3rd Author's Affiliation Nara Institute of Science and Technology(NAIST)
4th Author's Name Renyuan Zhang
4th Author's Affiliation Nara Institute of Science and Technology(NAIST)
5th Author's Name Yasuhiko Nakashima
5th Author's Affiliation Nara Institute of Science and Technology(NAIST)
Date 2022-01-24
Paper # VLD2021-61,CPSY2021-30,RECONF2021-69
Volume (vol) vol.121
Number (no) VLD-342,CPSY-343,RECONF-344
Page pp.pp.67-72(VLD), pp.67-72(CPSY), pp.67-72(RECONF),
#Pages 6
Date of Issue 2022-01-17 (VLD, CPSY, RECONF)