| Presentation | 2022-01-24 Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been implemented. In the arcitecture multiple types of engines which are specialized for di?erent purposes are conducted. As the advantage of SMT, the RISC-V SMT core allows multiple threads to be executed simultaneously at a lower cost than simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism in order to be installed in ”Chichibu” which is developed by ArchiTek as a multicore chip for edge AI. In this implementation, we have reduced the hardware resource usage to less than half of the previous implementation. Also the IPC has been improved by about 3% to 6% by using SMT even when delays in instruction and data memory is brought. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RISC-V / Simultaneous Multithreading / AI / Heterogeneous Processor |
| Paper # | VLD2021-57,CPSY2021-26,RECONF2021-65 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD / CPSY / IPSJ-ARC / IPSJ-SLDM |
|---|---|
| Conference Date | 2022/1/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Kentaro Sano(RIKEN) / Kazutoshi Kobayashi(Kyoto Inst. of Tech.) / Michihiro Koibuchi(NII) / Hiroshi Inoue(Kyushu Univ.) / Yuichi Nakamura(NEC) |
| Vice Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Tomonori Izumi(Ritsumeikan Univ.) / Minako Ikeda(NTT) / Kota Nakajima(Fujitsu Lab.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Secretary | Yoshiki Yamaguchi(NEC) / Tomonori Izumi(Tokyo Inst. of Tech.) / Minako Ikeda(Osaka Univ.) / Kota Nakajima(NEC) / Tomoaki Tsumura(JAIST) / (Hitachi) / (Univ. of Tokyo) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Ryukyu Univ.) / / Ryohei Kobayashi(Tsukuba Univ.) / Takaaki Miyajima(Meiji Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture / Special Interest Group on System and LSI Design Methodology |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of a RISC-V SMT Core in Virtual Engine Architecture |
| Sub Title (in English) | |
| Keyword(1) | RISC-V |
| Keyword(2) | Simultaneous Multithreading |
| Keyword(3) | AI |
| Keyword(4) | Heterogeneous Processor |
| 1st Author's Name | Hidetaro Tanaka |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 2nd Author's Name | Tomoaki Tanaka |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 3rd Author's Name | Keita Nagaoka |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 4th Author's Name | Ryosuke Higashi |
| 4th Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| 5th Author's Name | Tsutomu Sekibe |
| 5th Author's Affiliation | ArchiTek Corporation(ArchiTek) |
| 6th Author's Name | Shuichi Takada |
| 6th Author's Affiliation | ArchiTek Corporation(ArchiTek) |
| 7th Author's Name | Hironori Nakajo |
| 7th Author's Affiliation | Tokyo University of Agriculture and Technology(TUAT) |
| Date | 2022-01-24 |
| Paper # | VLD2021-57,CPSY2021-26,RECONF2021-65 |
| Volume (vol) | vol.121 |
| Number (no) | VLD-342,CPSY-343,RECONF-344 |
| Page | pp.pp.43-48(VLD), pp.43-48(CPSY), pp.43-48(RECONF), |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |